Datasheet

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2-, 3-, or 4-Cell Configuration
Watchdog Input (WDI)
GG Clock Never Starts
REG
GG 32-kHz Output
t
WDTINT
~ 700 mS
CHG, DSG, and
ZVCHG = OFF
EXT FET Control
GG Clock Stop
CHG, DSG, and
ZVCHG = OFF
t
WDWT
About 100 mS
REG
GG 32-kHz Output
Watchdog Sense
EXT FET Control
DSG and CHG FET Driver Control
bq29312A
SLUS629A – JANUARY 2005 – REVISED AUGUST 2005
FUNCTIONAL DESCRIPTION (continued)
In a 3-cell configuration, VC1 is shorted to VC2. In a 2-cell configuration, VC1 and VC2 are shorted to VC3.
The WDI input is required as a time base for delay timing when determining overload and short-circuit delay
periods and is used as part of the system watchdog.
Initially, the watchdog monitors the host oscillator start up; if there is no response from the host within 700 ms of
the bq29312A reaching its minimum operating voltage, then the bq29312A turns both CHG, DSG, and ZVCHG
FETs OFF.
Once the watchdog has been started during this wake-up period, it monitors the host for an oscillation stop
condition, which is defined as a period of 100 µs (typ), where no clock input is received. If an oscillator stop
condition is identified, then the watchdog turns the CHG, DSG, and ZVCHG FETs OFF. When the host clock
oscillation is started, WDF is released, but the flag is latched until LTCLR is toggled.
Figure 2. Watchdog Timing Chart—WDI Fault at Startup
Figure 3. Watchdog Timing Chart—WDI Fault After Startup
The bq29312A drives the DSG, CHG, and ZVCHG FET off if an OL or SC safety threshold is breached
depending on the current direction. The host can force any FET on or off only if the bq29312A integrated
protection control allows. The DSG and CHG FET drive gate-to-drain voltage is clamped to 15 V (typ).
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