Datasheet

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Cell Balance Control
Thermistor Drive Circuit (TOUT)
Open-Drain Drive Circuit (OD)
XALERT (XALERT)
Latch Clear (LTCLR)
bq29312A
SLUS629A – JANUARY 2005 – REVISED AUGUST 2005
FUNCTIONAL DESCRIPTION (continued)
Measuring V
O(3-4)
, V
O(2-3),
V
O(1-2),
• VC4 – VC5 = {V
O(4-5)
– V(
CELLOUT)
}/ K
(ACT)
• VC3 – VC4 = {V
O(3-4)
– V
(CELLOUT)
}/ K
(ACT)
• VC2 – VC3 = {V
O(2-3)
– V
(CELLOUT)
}/ K
(ACT)
• VC1 – VC2 = {V
O(1-2)
– V
(CELLOUT)
}/ K
(ACT)
The cell balance control allows a small bypass path to be controlled for any one series element. The purpose of
this bypass path is to reduce the current into any one cell during charging to bring the series elements to the
same voltage. Series resistors placed between the input pins and the positive series element nodes control the
bypass current value. Individual series element selection is made using bits 4 through 7 of the CELL_SEL
register.
The TOUT pin can be enabled to drive a thermistor from REG. The typical thermistor resistance is 10 k Ω at
25°C. The default-state is OFF to conserve power. The maximum output impedance is 100 Ω . TOUT is enabled
in FUNCTION CTL register (bit 5).
The open-drain output has 1-mA current source drive with a maximum output voltage of 25 V. The OD output is
enabled or disabled by OUTPUT CTL register (bit 4) and has a default state of OFF.
XALERT is driven low when an OL or SC current fault is detected, if the SLEEP pin changes state or a watchdog
fault occurs. To clear XALERT, toggle (from 0, set to 1 then reset to 0) OUTPUT CTL (bit 0), then read the
STATUS register.
When a current limit fault or watchdog timer fault occurs, the state is latched. To clear these faults, toggle (from
0, set 1 then reset to 0) LTCLR in the OUTPUT CTL register (bit 0).
Figure 1 is the LTCLR and XALERT clear example after sensing a short-circuit.
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