Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - battery management Surge/undervoltage protection Li-Ion, Li-Po TSSOP 24 Surface-mou

PW RTH

www.ti.com

FEATURES APPLICATIONS

DESCRIPTION

SYSTEM PARTITIONING DIAGRAM

LDO, Therm Output Drive & UVLO

Power Management

LDO, TOUT, and Power Mode control

Capacity Prediction <1% Error

SMBus

Pack +

Pack -

Discharge / Charge /

Precharge FETs

Cell and Pack

Voltage

Measurement

Precharge

FET Drive

2-Tier Overcurrent Protection

32-kHz Clock

Generator

bq2084

768 Bytes of

User Flash

Fuse

Level OV and

UV Protection

Pack Undervoltage

Power Mode

Control

Precharge Control

Delay Counters

Cell Balancing Algorithm and Control

Cell Balancing

Drive

System Interface

System Watchdog

Voltage Level Translator

System Interface

32 kHz

Power Mode Control

Fail-Safe Protection

Level OC

Protection

Temperature Measurement

<1% Error

INT

Supply V oltage

bq29312A

PCH FET Drive

RAM Registers

SBS v1.1 Data

bq29312 RAM/Comms Validation

2 nd Level Overvoltage Protection

XAlert

Sleep

Sense Resistor

(10 - 30 m W)

PF Input

bq29312A

SLUS629A – JANUARY 2005 – REVISED AUGUST 2005

TWO-CELL, THREE-CELL, AND FOUR-CELL LITHIUM-ION OR

LITHIUM-POLYMER BATTERY PROTECTION AFE

• Notebook PCs

• 2-, 3-, or 4-Cell Series Protection Control

• Medical and Test Equipment

• Can Directly Interface With the bq2084 Gas

• Portable Instrumentation

Gauges

• Provides Individual Cell Voltages and Battery

Voltage to Battery Management Host

The bq29312A is a 2-, 3-, or 4-cell lithium-ion battery

• Integrated Cell Balancing Drive

pack protection analog front end (AFE) IC that

• I

C Compatible User Interface Allows Access

incorporates a 3.3-V, 25-mA low-dropout regulator

to Battery Information

(LDO). The bq29312A also integrates an I

C compat-

• Programmable Threshold and Delay for

ible interface to extract battery parameters such as

Overload and Short Circuit During Charge and

cell voltages and control output status. Other par-

Discharge

ameters such as current protection thresholds and

delays can be programmed into the bq29312A to

• System Alert Interrupt Output

increase the flexibility of the battery management

• Host Control Can Initiate Sleep Power Mode

system.

and Ship Mode

The bq29312A provides safety protection for over-

• Integrated 3.3-V, 25-mA LDO

charge, overload, short-circuit, overvoltage, and

• Supply Voltage Range From 4.5 V to 25 V

undervoltage conditions with the battery management

host. In overload and short-circuit conditions, the

• Low Supply Current of 60-µA Typical

bq29312A turns the FET drive off autonomously

• bq29312A is 100% specification compatible

dependant on the internal configuration setting.

with the bq29312

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (38 pages)

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PW RTH bq29312A www.ti.
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bq29312A www.ti.com SLUS629A – JANUARY 2005 – REVISED AUGUST 2005 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (Continued) The communications interface allows the host to observe and control the current status of the bq29312A.
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bq29312A www.ti.com SLUS629A – JANUARY 2005 – REVISED AUGUST 2005 RECOMMENDED OPERATING CONDITIONS MIN Supply Voltage (BAT or PACK) VI(STARTUP) Start-up voltage (PACK) VIH Input voltage range MAX 25 5.0 VC1, VC2, VC3, VC4 VI NOM 4.5 (1) UNIT V V 0 BAT SR1, SR2 –0.5 0.5 VC5 –0.5 3.0 VCn – VC(n+1), (n = 1, 2, 3, 4 ) 0 5.0 PMS 0 PACK SLEEP 0 REG 0.8 × REG REG 0 0.2 × REG V(PACK) – 0.2 V(PACK) 0 0.
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bq29312A www.ti.com SLUS629A – JANUARY 2005 – REVISED AUGUST 2005 ELECTRICAL CHARACTERISTICS TA = 25°C, C(REG) = 4.7 µF, BAT = 14 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT ICC1 Supply current 1 No load at REG, TOUT, XALERT, SCLK, and SDATA. ZVCHG = off ,VMEN = on, WDI no clock, Select VC5 = VC4 = 0 V TA = –25°C to 85°C 60 90 ICC2 Supply current 2(Depends of VM topology selected) No load at REG, TOUT, XALERT, SCLK, and SDATA.
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bq29312A www.ti.com SLUS629A – JANUARY 2005 – REVISED AUGUST 2005 ELECTRICAL CHARACTERISTICS (Continued) TA = 25°C, C(REG) = 4.
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bq29312A www.ti.com SLUS629A – JANUARY 2005 – REVISED AUGUST 2005 AC ELECTRICAL CHARACTERISTICS TA = 25°C, C(REG) = 4.7 µF, BAT = 14 V (unless otherwise noted) PARAMETER TEST CONDITION t(WDTINT) WDT start-up detect time t(WDWT) WDT detect time MIN NOM MAX 250 700 2000 UNIT ms 100 µs AC TIMING SPECIFICATIONS (I2C COMPATIBLE SERIAL INTERFACE) PARAMETER MIN MAX UNIT 1000 ns 300 ns tr SCLK SDATA rise time tf SCLK SDAT fall time tw(H) SCLK pulse width high 4.
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bq29312A www.ti.com SLUS629A – JANUARY 2005 – REVISED AUGUST 2005 PIN ASSIGNMENTS PW PACKAGE (TOP VIEW) VC1 DSG BAT OD PMS PACK 24 23 22 21 20 19 18 17 16 15 14 13 OD PMS PACK ZVCHG CHG SLEEP REG TOUT XALERT GND SDATA SCLK ZVCHG CHG SLEEP REG TOUT XALERT VC2 VC3 VC4 VC5 SR1 SR2 WDI CELL GND SCLK SDATA GND 1 2 3 4 5 6 7 8 9 10 11 12 BAT DSG VC1 VC2 VC3 VC4 VC5 SR1 SR2 WDI CELL GND RTH PACKAGE (TOP VIEW) Terminal Functions TERMINAL NAME PIN NO.
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bq29312A www.ti.com SLUS629A – JANUARY 2005 – REVISED AUGUST 2005 FUNCTIONAL BLOCK DIAGRAM PACK- GG VDD PACK+ R(ZVCHG) C (REG) PMS ZVCHG REG 0.2-A Current Source CHG DSG BAT ZVCHG_ON Gate Driver CHG_ON DSG_ON + _ - PACK FET Logic REG 3.
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bq29312A www.ti.com SLUS629A – JANUARY 2005 – REVISED AUGUST 2005 STATE DIAGRAM No Power SHIP MODE EXIT BY POWER SUPPLY TO PACK POWER SUPPLY TO PACK INITIALIZE FETS: OFF(*2) REG: start Working I2C: OFF CURRENT FAULT : OFF CELL MONITOR : OFF WATCHDOG : OFF THERMISTOR PWER CTRL : OFF REG >2.4 V IFAULT RESET CURRENT LATCH HOST FAULT MODE FETS: OFF REG: ON I2C: ON CURRENT FAULT : OFF CELL MONITOR : OFF WATCHDOG : ON THERMISTOR PWER CTRL : OFF REG < 2.
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bq29312A www.ti.com SLUS629A – JANUARY 2005 – REVISED AUGUST 2005 FUNCTIONAL DESCRIPTION Low-Dropout Regulator (REG) The inputs for this regulator can be derived from the battery cell stack (BAT) or the pack positive terminal (PACK). The output is typically 3.3 V with the minimum output capacitance for stable operation is 4.7 µF and is also internally current limited. During normal operation, the regulator limits output current to typically 50 mA.
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bq29312A www.ti.com SLUS629A – JANUARY 2005 – REVISED AUGUST 2005 FUNCTIONAL DESCRIPTION (continued) Cell Voltage The cell voltage is translated to allow a system host to measure individual series elements of the battery. The series element voltage is translated to a GND-based voltage equal to 0.15 ±0.002 of the series element voltage. This provides a range from 0 V to 4.5 V. The translation output is inversely proportional to the input using the following equation.
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bq29312A www.ti.com SLUS629A – JANUARY 2005 – REVISED AUGUST 2005 FUNCTIONAL DESCRIPTION (continued) Measuring VO(3-4) , VO(2-3), VO(1-2), • VC4 – VC5 = {VO(4-5)– V(CELLOUT)}/ K(ACT) • VC3 – VC4 = {VO(3-4)– V(CELLOUT)}/ K(ACT) • VC2 – VC3 = {VO(2-3)– V(CELLOUT)}/ K(ACT) • VC1 – VC2 = {VO(1-2)– V(CELLOUT)}/ K(ACT) Cell Balance Control The cell balance control allows a small bypass path to be controlled for any one series element.
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bq29312A www.ti.com SLUS629A – JANUARY 2005 – REVISED AUGUST 2005 FUNCTIONAL DESCRIPTION (continued) I2C OUTPUT CTRL (b2-b1) DSG, CHG OUTPUT CTRL (b3) XZVCHG LTCLR Write = 1 LTCLR Write = 0 Read STATUS Register Status Disable Access Enable Status Disable Access Enable OUTPUT CTRL (b0) LTCLR Short Current Timeout in Discharge Direction STATUS (b0) SCDSG XALERT Pin Figure 1.
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bq29312A www.ti.com SLUS629A – JANUARY 2005 – REVISED AUGUST 2005 FUNCTIONAL DESCRIPTION (continued) 2-, 3-, or 4-Cell Configuration In a 3-cell configuration, VC1 is shorted to VC2. In a 2-cell configuration, VC1 and VC2 are shorted to VC3. Watchdog Input (WDI) The WDI input is required as a time base for delay timing when determining overload and short-circuit delay periods and is used as part of the system watchdog.
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bq29312A www.ti.com SLUS629A – JANUARY 2005 – REVISED AUGUST 2005 FUNCTIONAL DESCRIPTION (continued) The default-state of the CHG and DSG FET drive is off, when PMS = GND. A host can control the FET drive by programming OUTPUT CTL (b3...b1) where b1 is used to control the discharge FET, b2 is used to control the charge FET, and b3 is used to control the ZVCHG FET. These controls are only valid when not in the initialized state.
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bq29312A www.ti.com SLUS629A – JANUARY 2005 – REVISED AUGUST 2005 Communications The I2C compatible serial communications provides read and write access to the bq29312A data area. The data is clocked via separate data (SDATA) and clock (SCLK) pins. The bq29312A acts as a slave device and does not generate clock pulses. Communication to the bq29312A is provided from GPIO pins or an I2C supporting port of a host system controller.
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bq29312A www.ti.com SLUS629A – JANUARY 2005 – REVISED AUGUST 2005 Register Map The bq29312A has nine addressable registers. These registers provide status, control, and configuration information for the battery protection system. Table 3.
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bq29312A www.ti.com SLUS629A – JANUARY 2005 – REVISED AUGUST 2005 The OUTPUT CTL register controls the outputs of the bq29312A and can be used to clear certain states. OUTPUT CTL b0 (LTCLR): When a current limit fault or watchdog timer fault is latched, this bit releases the fault latch when toggled from 0 to 1 and back to 0 (default =0). 0 = (default) 0->1 ->0 clears the fault latches OUTPUT CTL b1 (DSG): This bit controls the external discharge FET.
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bq29312A www.ti.com SLUS629A – JANUARY 2005 – REVISED AUGUST 2005 FUNCTION CTL: Function Control Register FUNCTION CTL REGISTER (0x03) 7 6 5 4 3 2 1 0 0 0 TOUT XSCD SSCC XOL PACKOUT VMEN The FUNCTION CTL register enables and disables functions of the bq29312A. FUNCTION CTL b0 (VMEN): This bit enables or disables the cell and battery voltage monitoring function. 0 = disable voltage monitoring (default). CELL output is pulled down to GND level. 1 = enable voltage monitoring.
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bq29312A www.ti.com SLUS629A – JANUARY 2005 – REVISED AUGUST 2005 CELL_SEL b4–b7 (CB0–CB3): These 4 bits select the series cell for cell balance bypass path. CELL SEL b4 (CB0): This bit enables or disables the bottom series cell balance charge bypass path. 0 = disable bottom series cell balance charge bypass path (default). 1 = enable bottom series cell balance charge bypass path. CELL SEL b5 (CB1): This bit enables or disables the second lowest series cell balance charge bypass path.
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bq29312A www.ti.com SLUS629A – JANUARY 2005 – REVISED AUGUST 2005 This register selects the short-circuit threshold voltage and delay for charge. SCC(b3–b0) : These bits select the value of the short-circuit voltage threshold with 0000 as the default. SCC(b3–b0) with corresponding SC threshold voltage 0000 0.100 V 0100 0.200 V 1000 0.300 V 1100 0.400 V 0001 0.125 V 0101 0.225 V 1001 0.325 V 1101 0.425 V 0010 0.150 V 0110 0.250 V 1010 0.350 V 1110 0.450 V 0011 0.175 V 0111 0.
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bq29312A www.ti.com SLUS629A – JANUARY 2005 – REVISED AUGUST 2005 APPLICATION INFORMATION Precharge and 0-V Charging—Theory of Operation In order to charge, the charge FET (CHG-FET) must be turned on to create a current path. When the V(BAT) is 0 V and CHG-FET = ON, the V(PACK) is as low as the battery voltage. In this case, the supply voltage for the device is too low to operate.
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bq29312A www.ti.com SLUS629A – JANUARY 2005 – REVISED AUGUST 2005 APPLICATION INFORMATION (continued) In order to pass 0 V or precharge current, an appropriate gate-source voltage V(GS), for ZVCHG-FET must be applied. Here, V(PACK) can be expressed in terms of V(GS) as follows: V(PACK) = V(ZVCHG) + V(GS) (ZVCHG-FET gate - source voltage) ID Point B Point A Precharge Current VGS VDS Figure 8.
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bq29312A www.ti.com SLUS629A – JANUARY 2005 – REVISED AUGUST 2005 APPLICATION INFORMATION (continued) 20 18 16 V(PACK) 14 Voltage - V V(ZVCHG)= V(PACK) - 8 V V(BAT) 12 10 8 6 4 V(ZVCHG)= V(PACK) / 2 2 3.5 V 0 0 4 8 12 t - Time - mS 16 20 Figure 9. Voltage Transition at ZVCHG, PACK, and BAT As V(PACK) exceeds 7 V, V(ZVCHG) = V(PACK)/2. However, V(ZVCHG) is maintained to limit the voltage between PACK and ZVCHG at a maximum of 8 V(typ).
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bq29312A www.ti.com SLUS629A – JANUARY 2005 – REVISED AUGUST 2005 APPLICATION INFORMATION (continued) V(PACK) 3.5 V+VGS(ZVCHGFET) 0V 3.3 V 0V REG ZVCHG FET = OFF ON V = VPACK*(1/2) ZVCHG 3.5 V (typ.) 0V OFF CHG FET = ON GHD ”L” (1 V) OFF CHG FET = ON DSG ”L” (1 V) Battery Voltage 0V Charge Current Fast Charge Current 0 V and Precharge Current 0A 0 V Charge Mode Precharge Mode Fast Charge Mode Figure 10.
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bq29312A www.ti.com SLUS629A – JANUARY 2005 – REVISED AUGUST 2005 APPLICATION INFORMATION (continued) The disadvantages is that during 0-V charging, bq29312A is inactive. The device does not protect the battery and does not update battery information (now is 0 V charging) to the PC. There are two advantage of this configuration: 1. The voltage between BAT and PACK is lower. Higher precharge current is allowed due to less heat loss in the FET, and no external resistor is required. 2.
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bq29312A www.ti.com SLUS629A – JANUARY 2005 – REVISED AUGUST 2005 APPLICATION INFORMATION (continued) 0.7 V 0V V(PACK) Host = Inactive Host = Active REG 3.3 V 0V PMS CHG Set to ”L” as PMS = PACK 0V Set to ”L” by Host ”L” (1 V) 0V DSG Host Sets DSG-FET to ON ”L” (1 V) Battery Voltage 0V Charge Current Fast Charge Current 0 V and Precharge Current 0A 0 V Precharge Mode Fast Charge Mode Figure 12.
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bq29312A www.ti.com SLUS629A – JANUARY 2005 – REVISED AUGUST 2005 APPLICATION INFORMATION (continued) R(PCHG) Charger PCHG-FET CC DC Input I(FASTCHG) DSG-FET CHG-FET DSG CHG PACK OD BAT bq29312A Battery Pack+ CV ZVCHG PMS REG SCLK SDATA 4.7 mF I(FASTCHG) = Fast Current Host Figure 13. Precharge FET Mode Circuit Diagram The PCHG-FET is driven by the OD output, and the resister R(PCHG) in the precharge path limits the precharge current. When OD = GND, then the PCHG-FET is ON.
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bq29312A www.ti.com SLUS629A – JANUARY 2005 – REVISED AUGUST 2005 APPLICATION INFORMATION (continued) In this configuration, attention must be paid to high power consumption in the PCHG-FET and the series resistor R(PCHG). The highest power is consumed when VBAT = 0 V, where it is the highest differential between the PACK and BAT pins. For example, the power consumption in 4-series cells with 17.4 V fast charge voltage and R(PCHG) = 188 Ω is expressed below. • IPCHG = (17.4 V – 0.0 V)/188 Ω = 92.
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bq29312A www.ti.com SLUS629A – JANUARY 2005 – REVISED AUGUST 2005 APPLICATION INFORMATION (continued) Summary The three types of 0-V charge options available with the bq29312A are summarized in Table 4. Table 4.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant BQ29312APWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 BQ29312ARTHR VQFN RTH 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) BQ29312APWR BQ29312ARTHR TSSOP PW 24 2000 367.0 367.0 38.0 VQFN RTH 24 3000 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.