Datasheet

OUT
Cell Voltage
V
PROTECT
L
H
t
d
VC2
-
VC
1,
VC1 GND
-
V
PROTECT
-
HYS
V
bq29200
bq29209
www.ti.com SLUSA52A –SEPTEMBER 2010–REVISED NOVEMBER 2010
Figure 6. Timing for Overvoltage Sensing
CELL CONNECTION SEQUENCE
NOTE
Before connecting the cells, propagate the overvoltage delay timing capacitor, C
CD
.
The recommended cell connection sequence begins from the bottom of the stack, as follows:
1. GND
2. VC1
3. VC2
While not advised, connecting the cells in a sequence other than that described above does not result in errant
activity on the OUT pin. For example:
1. GND
2. VC2 or VC1
3. Remaining VCx pin
CELL BALANCE ENABLE CONTROL
To avoid prematurely discharging the cells, it is recommended to turn off (pull high) the active-low Cell Balance
Enable Control pin at lower State of Charge (SOC) levels.
CELL IMBALANCE AUTO-DETECTION (VIA CELL VOLTAGE)
The V
MM_DET_ON
and V
MM_DET_OFF
specifications are calibrated where VDD = VC2 = 7.6 V and VC1 = 3.8 V. The
recommended range of cell balancing is VC2 and VDD between 6.0 V and 8.4 V, and VC1 between 3.0 V and
4.2 V. Below VDD = 6.0 V, it is recommended to pull CB_EN high to disable the cell balancing function.
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