Datasheet

bq28400
SLUSA61A –OCTOBER 2010–REVISED DECEMBER 2010 www.ti.com
THERMAL INFORMATION
bq28400
THERMAL METRIC
(1)
PW UNITS
20 PINS
q
JA
Junction-to-ambient thermal resistance
(2)
91.7
q
JC(top)
Junction-to-case(top) thermal resistance
(3)
20.4
q
JB
Junction-to-board thermal resistance
(4)
45.6
°C/W
y
JT
Junction-to-top characterization parameter
(5)
0.5
y
JB
Junction-to-board characterization parameter
(6)
43.3
q
JC(bottom)
Junction-to-case(bottom) thermal resistance
(7)
n/a
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, y
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining q
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, y
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining q
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature (unless otherwise noted)
(1)
Value/Unit
Supply voltage range, V
MAX
PACK w.r.t. V
SS
–0.3 to 34 V
V
VC2
–0.3 to V
VC2
+ 8.5 or 34 V,
VC1, BAT
whichever is lower
VC2 V
VSRP
–0.3 to V
VSRP
+ 8.5 V
SRP, SRN –0.3 to V
REG27
General Purpose open-drain I/O pins: SMBD, SMBC V
SS
–0.3 V to 6 V
Input voltage range, V
IN
General Purpose push-pull I/O pins: TS1, PRES, CB_EN –0.3 V to V
REG27
+ 0.3 V
Input voltage range to all other pins, V
IN
relative to V
SS
–0.3 V to V
REG27
+ 0.3 V
DSG, CHG, ZVCHG –0.3 to BAT
–0.3 to [BAT or PACK] (whichever is
FUSE
lower)
RBI, REG27 –0.3 to 2.75 V
Maximum Operational VSS current,
50 mA
I
SS
Ambient Temperature, T
A
–20 to 110°C
Storage temperature range, T
STG
–65 to 150°C
All pins except VC1 and VC2 2 kV
ESD Human Body Model
(2)
VC1 and VC2 1 kV
ESD Machine Model All pins 200 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin.
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