Datasheet

1
2
BAT
VC1
3
TS1
4
SRN RBI
5
6
CB_EN
7
8
VSS
PACK
DSG
SMBC
SRP
15
16
9
10
17
18
20
19
VSS
REG27
ZVCHG
FUSE
CHG
NCSMBD
VC2
13
14
12
11
PRES
bq28400
www.ti.com SLUSA61A –OCTOBER 2010–REVISED DECEMBER 2010
bq28400
PW PACKAGE
(TOP VIEW)
PIN FUNCTIONS
PIN NAME PIN NUMBER TYPE
(1)
DESCRIPTION
BAT 1 P Alternate supply input
DSG 2 O P-channel discharge FET gate drive
Sense input for the most positive cell. Also external cell balancing drive output for the
VC1 3 AI
most positive cell
Sense input for the lowest cell. Also external cell balancing drive output for the lowest
VC2 4 AI
cell
VSS 5 P Device ground
SRP 6 AI Differential Coulomb Counter input or SRP oversampled ADC input
SRN 7 AI Differential Coulomb Counter input or SRN oversampled ADC input
TS1 8 I Thermistor 1 input. Connect NTC from this pin to VSS pin
CB_EN 9 O Output signal to control cell balancing
SMBD 10 I/OD SBS data
NC 11 — No connection, leave floating
SMBC 12 I/OD SBS clock
PRES 13 I System present
RAM backup pin to provide backup potential to the internal DATA RAM if power is
RBI 14 P
momentarily lost, by using a capacitor attached between RBI and VSS
VSS 15 P Device ground
REG27 16 P 2.7-V regulator. Connect a capacitor between REG27 and VSS
FUSE 17 O Push-pull fuse circuit drive
ZVCHG 18 O P-channel precharge FET gate drive
CHG 19 O P-channel charge FET gate drive
PACK 20 P Alternate supply input
(1) P = Power Connection, O = Digital Output, AI = Analog Input, I = Digital Input, I/OD = Digital Input/Output
Copyright © 2010, Texas Instruments Incorporated 3
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