Datasheet

CHG FET DSG FET
PACK+
DSG
Cell 1
Q
1
1 KW
0.1µF
0.1µF
Cell 2
Q
2
1 KW
100 W
100 W
VC1
VC2
VSS
NOTE: Q1 and Q2 are Si1023
type P-CH FETs
CHG
Fuse
RSNS
CHG
DSG
FUSE
PRES
VC2
VC1
BAT
PACK
VSS
REG27 RB1
SMBC
SMBD
SRP
SRN
bq28400
TS1
VSS
PACK
–
PACK +
CB_EN
ZVCHG
VC2
VC1
VC1_CB
CD GND
CB_EN
VDD
OUT
bq29200
1k
220
k
1k
1k
360
0.22
µF
0.1
µF
0.1
µF
0.1
µF
bq28400
www.ti.com SLUSA61A –OCTOBER 2010–REVISED DECEMBER 2010
Figure 3. Internal Cell Balancing Control Circuit
Figure 4. External Auto Cell Balancing Circuit
Layout Recommendations
For an accurate differential voltage sensing, the VSS ground should be connected directly to the most negative
terminal of the battery stack, not to the positive side of the sense resistor. This minimizes the voltage drop across
the PCB trace.
Copyright © 2010, Texas Instruments Incorporated 19
Product Folder Link(s): bq28400