Datasheet
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Pack Configuration (PKCFG) — Address 0x7C
Initial Max Load Current (IMLC) — Address 0x7D
bq27000 , bq27200
SLUS556D – SEPTEMBER 2004 – REVISED MARCH 2006
TAPER[7] should be set to 1 to enable the automatic aging of the LMD full capacity value. If this feature is
enabled, LMD is reduced by Design Capacity/1024 every time CYCL increments by 2 and every time that a
cumulative NAC self-discharge estimate reduction of 1.56% has been made without charging the battery to full. If
TAPER[7] is set to 0, there is no LMD reduction with cycle count or self-discharge.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
NAME GPIEN QV1 QV0 BOFF(2) BOFF(1) BOFF(0) DCFIX TCFIX
GPIEN Allows the pack manufacturer to set the state of the GPIO pin on initial power up. If the bit is 0, the
GPIEN bit is cleared on reset and the GPIO pin acts as a high-impedance output. If the bit is 1, the
GPIEN bit is set on reset and the GPIO pin acts as an input. The state of the GPIO pin can then be
read through the GPSTAT bit in the MODE register.
QV1 & QV0 These bits set the minimum qualification voltage for charge termination. The termination voltage
thresholds are set as listed in Table 3 .
Table 3. Charge Termination Voltage Settings
QV1 QV0 Voltage (mV)
0 0 3968
0 1 4016
1 0 4064
1 1 4112
BOFF These bits are used to store a typical board offset value for the gauge. This value is added to the
internal offset measurement and the total applied as an offset correction for the charge and
discharge coulometric measurements made by the DSCC. This is a 2s-complement signed number
with a value of 2.45 µV per bit.
Table 4. Board Offset Voltage Settings
Board Offset BOFF(2) BOFF(1) BOFF(0)
7.35 µV 0 1 1
4.9 µV 0 1 0
2.45 µV 0 0 1
0 0 0 0
-2.45 µV 1 1 1
-4.9 µV 1 1 0
-7.35 µV 1 0 1
-9.8 µV 1 0 0
DCFIX Fixed discharge compensation. Normal discharge rate compensation (DCOMP register) is used if
this bit is set to 0. If this bit is set to 1, the device assumes a fixed value of 0x42 for DCOMP, giving
a discharge rate compensation gain of 6.25% with a compensation threshold of C/4. Setting the bit
to 1 frees the EEPROM location of 0x7E for use as a programmable identification byte.
TCFIX Fixed temperature compensation. Normal temperature compensation (TCOMP register) is used if
this bit is set to 0. If this bit is set to 1, the device assumes a fixed value of 0x7C for TCOMP, giving
a temperature compensation gain of 0.68% of Design Capacity/ ° C with an offset of 12 ° C. Setting
this bit to 1 frees the EEPROM location of 0x7F for use as a programmable identification byte.
This register contains the scaled, end-equipment-design maximum current. On a full reset or POR, this value is
transferred to the MLI register and used to calculate max load time-to-empty. The device learns a new maximum
load if the current exceeds the initial maximum load. The equation for programming this value is:
IMLC = Design Max Current (mA) * R
S
(m Ω )/457 µV
where R
S
is the value of the sense resistor used in the system.
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