Datasheet

A AS 0ADDR[6:0] CMD[7:0]
Sr
1ADDR[6:0] A DATA [7:0] A DATA [7:0] PN
A AS A0 PADDR[6:0] CMD[7:0] DATA [7:0] DATA [7:0] A 66ms
A AS 0ADDR[6:0] CMD[7:0]
Sr
1ADDR[6:0] A DATA [7:0] A DATA [7:0] A
DATA [7:0] A DATA [7:0] PN
Waitingtimebetweencontrolsubcommandandreadingresults
Waitingtimebetweencontinuousreadingresults
66ms
66ms
bq27541-G1
www.ti.com SLUSAL6C –NOVEMBER 2011–REVISED OCTOBER 2012
I
2
C Command Waiting Time
To make sure the correct results of a command with the 400KHz I
2
C operation, a proper waiting time should be
added between issuing command and reading results. For subcommands, the following diagram shows the
waiting time required between issuing the control command the reading the status with the exception of the
checksum command. A 100ms waiting time is required between the checksum command and reading result. For
read-write standard commands, a minimum of 2 seconds is required to get the result updated. For read-only
standard commands, there is no waiting time required, but the host should not issue all standard commands
more than two times per second. Otherwise, the gauge could result in a reset issue due to the expiration of the
watchdog timer.
I
2
C Clock Stretching
I
2
C clock stretches can occur during all modes of fuel gauge operation. In the SLEEP and HIBERNATE modes, a
short clock stretch will occur on all I2C traffic as the device must wake-up to process the packet. In NORMAL
and SLEEP+ modes, clock stretching will only occur for packets addressed for the fuel gauge. The timing of
stretches will vary as interactions between the communicating host and the gauge are asynchronous. The I
2
C
clock stretches may occur after start bits, the ACK/NAK bit and first data bit transmit on a host read cycle. The
majority of clock stretch periods are small (<= 4mSec) as the I2C interface peripheral and CPU firmware perform
normal data flow control. However, less frequent but more significant clock stretch periods may occur when data
flash (DF) is being written by the CPU to update the resistance (Ra) tables and other DF parameters such as
Qmax. Due to the organization of DF, updates need to be written in data blocks consisting of multiple data bytes.
An Ra table update requires erasing a single page of DF, programming the updated Ra table and a flag. The
potential I
2
C clock stretching time is 24ms max. This includes 20ms page erase and 2ms row programming time
(x2 rows). The Ra table updates occur during the discharge cycle and at up to 15 resistance grid points that
occur during the discharge cycle.
A DF block write typically requires a max of 72ms. This includes copying data to a temporary buffer and updating
DF. This temporary buffer mechanism is used to protect from power failure during a DF update. The first part of
the update requires 20ms time to erase the copy buffer page, 6 ms time to write the data into the copy buffer and
the program progress indicator (2ms for each individual write). The second part of the update is writing to the DF
and requires 44ms DF block update time. This includes a 20ms each page erase for two pages and 2ms each
row write for two rows.
In the event that a previous DF write was interrupted by a power failure or reset during the DF write, an
additional 44ms max DF restore time is required to recover the data from a previously interrupted DF write. In
this power failure recovery case, the total I
2
C clock stretching is 116ms max.
Another case where I
2
C clock stretches is at the end of discharge. The update to the last discharge data will go
through the DF block update twice because two pages are used for the data storage. The clock stretching in this
case is 144ms max. This occurs if there has been a Ra table update during the discharge.
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