Datasheet

S ADDR[6:0] 0 A CMD[7:0]
A Sr
ADDR[6:0]
1 A
DATA[7:0]
A
...
DATA[7:0]
N P
Address
0x7F
DataFrom
addr0x7F
DataFrom
addr0x00
S
ADDR[6:0]
0 A
CMD[7:0]
A
A
N
P
DATA[7:0]
DATA[7:0]
...
N
S ADDR[6:0] 0 A
CMD[7:0]
N P
S ADDR[6:0] 0 A CMD[7:0] A DATA[7:0] A P
S ADDR[6:0] 0 A CMD[7:0] A DATA[7:0] A P S ADDR[6:0] 1 A DATA[7:0] N P
S
ADDR[6:0]
0 A
CMD[7:0]
A Sr
ADDR[6:0] 1 A DATA[7:0]
N P
S ADDR[6:0] 0 A CMD[7:0]
A Sr
ADDR[6:0]
1 A
DATA[7:0]
A
...
DATA[7:0]
N P
(d)
(c)
(a) (b)
HostGenerated FuelGaugeGenerated
bq27541-G1
SLUSAL6C –NOVEMBER 2011–REVISED OCTOBER 2012 www.ti.com
I
2
C INTERFACE
The fuel gauge supports the standard I
2
C read, incremental read, one-byte write quick read, and functions. The
7-bit device address (ADDR) is the most significant 7 bits of the hex address and is fixed as 1010101. The 8-bit
device address is therefore 0xAA or 0xAB for write or read, respectively.
Figure 4. Supported I
2
C formats: (a) 1-byte write, (b) quick read, (c) 1 byte-read, and (d) incremental read
(S = Start, Sr = Repeated Start, A = Acknowledge, N = No Acknowledge, and P = Stop).
The "quick read" returns data at the address indicated by the address pointer. The address pointer, a register
internal to the I2C communication engine, increments whenever data is acknowledged by the bq27541-G1 or the
I2C master. "Quick writes" function in the same manner and are a convenient means of sending multiple bytes to
consecutive command locations (such as two-byte commands that require two bytes of data).
Attempt to write a read-only address (NACK after data sent by master):
Attempt to read an address above 0x7F (NACK command):
Attempt at incremental writes (NACK all extra data bytes sent):
Incremental read at the maximum allowed read address:
The I
2
C engine releases both SDA and SCL if the I
2
C bus is held low for t
(BUSERR)
. If the fuel gauge was holding
the lines, releasing them frees the master to drive the lines. If an external condition is holding either of the lines
low, the I
2
C engine enters the low-power sleep mode.
I
2
C Time Out
The I2C engine will release both SDA and SCL if the I2C bus is held low for about 2 seconds. If the bq27541-G1
was holding the lines, releasing them will free for the master to drive the lines.
40 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Links: bq27541-G1