Datasheet

Host generated
A AS 0ADDR[6:0] CMD[7:0] Sr 1ADDR[6:0] A DATA [7:0] A DATA [7:0] PN. . .
(d) incremental read
A AS 0ADDR[6:0] CMD [7:0] Sr 1ADDR[6:0] A DATA [7:0] PN
(c) 1- byte read
A AS A0 PADDR[6:0] CMD [7:0] DATA [7:0]
(a) 1-byte write
(b) quick read
S 1ADDR[6:0] A DATA [7:0] PN
Gauge generated
. . .A AS A0 PADDR[6:0] CMD[7:0] DATA [7:0] DATA [7:0] A A
(e) incremental write
(S = Start, Sr = Repeated Start , A = Acknowledge , N = No Acknowledge , and P = Stop).
bq27530-G1
www.ti.com SLUSAL5 –DECEMBER 2012
COMMUNICATIONS
I
2
C INTERFACE
The bq27530-G1 supports the standard I
2
C read, incremental read, quick read, one byte write, and incremental
write functions. The 7 bit device address (ADDR) is the most significant 7 bits of the hex address and is fixed as
1010101. The first 8-bits of the I
2
C protocol will; therefore, be 0xAA or 0xAB for write or read, respectively.
The “quick read” returns data at the address indicated by the address pointer. The address pointer, a register
internal to the I
2
C communication engine, will increment whenever data is acknowledged by the bq27530-G1 or
the I
2
C master. “Quick writes” function in the same manner and are a convenient means of sending multiple
bytes to consecutive command locations (such as two-byte commands that require two bytes of data)
The following command sequences are not supported:
Attempt to write a read-only address (NACK after data sent by master):
Attempt to read an address above 0x6B (NACK command):
I
2
C Time Out
The I
2
C engine will release both SDA and SCL if the I
2
C bus is held low for 2 seconds. If the bq27530-G1 was
holding the lines, releasing them will free them for the master to drive the lines. If an external condition is holding
either of the lines low, the I
2
C engine will enter the low power sleep mode.
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