Datasheet

7 COMMUNICATIONS
7.1 I
2
C INTERFACE
Hostgenerated
A AS 0ADDR[6:0] CMD[7:0] Sr 1ADDR[6:0] A DATA [7:0] A DATA [7:0] PN...
(d) incrementalread
A AS 0ADDR[6:0] CMD[7:0] Sr 1ADDR[6:0] A DATA [7:0] PN
(c) 1- byteread
A AS A0 PADDR[6:0] CMD[7:0] DATA [7:0]
(a) 1-bytewrite
(b) quickread
S 1ADDR[6:0] A DATA [7:0] PN
bq27500/1 generated
...A AS A0 PADDR[6:0] CMD[7:0] DATA [7:0] DATA [7:0] A A
(e) incrementalwrite
(S = Start, Sr = RepeatedStart , A = Acknowledge , N = No Acknowledge , andP = Stop).
bq27500
bq27501
System-Side Impedance Track™ Fuel Gauge
www.ti.com SLUS785D – SEPTEMBER 2007 – REVISED APRIL 2008
The 27500/1 supports the standard I
2
C read, incremental read, quick read, one byte write, and
incremental write functions. The 7 bit device address (ADDR) is the most significant 7 bits of the hex
address and is fixed as 1010101. The 8-bit device address will therefore be 0xAA or 0xAB for write or
read, respectively.
The “quick read” returns data at the address indicated by the address pointer. The address pointer, a
register internal to the I
2
C communication engine, will increment whenever data is acknowledged by the
bq27500/1 or the I
2
C master. “Quick writes” function in the same manner and are a convenient means of
sending multiple bytes to consecutive command locations (such as two-byte commands that require two
bytes of data)
The following command sequences are not supported:
Attempt to write a read-only address (NACK after data sent by master):
Attempt to read an address above 0x6B (NACK command):
The I
2
C engine will release both SDA and SCL if the I
2
C bus is held low for t
(BUSERR)
. If the bq27500/1 was
holding the lines, releasing them will free the master to drive the lines. If an external condition is holding
either of the lines low, the I
2
C engine will enter the low power sleep mode.
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