Datasheet

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TIMING DIAGRAMS
1-Bit
R/W
UDG−03039
Break 7−Bit Address 8−Bit Data
t
(B)
t
(BR)
t
(HW1)
t
(HW0)
t
(CYCH)
t
(RSPS)
t
(CYCD)
t
(DW0)
t
(DW1)
(a) Break and Break Recovery
(b) Host Transmitted Bit (c) bqJUNIOR Transmitted Bit
(d) bqJUNIOR to Host Response
UDG−04122
t
su(STA)
SCL
SDA
REPEATED STOP START
t
r
t
w(H)
t
w(L)
t
h(DAT)
t
su(DAT)
t
f
t
su(STOP)
t
(BUF)
t
r
t
f
t
d(STA)
START
bq27010 , bq27210
SLUS707B – APRIL 2006 – REVISED JANUARY 2007
Figure 1. HDQ Bit Timing Diagram
Figure 2. I
2
C Timing Diagram
5
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