Datasheet

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SLUS491 – JULY 2001
15
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APPLICATION INFORMATION
temperature and clear register (continued)
The clear bit locations are
TMP/CLR BITS
7 6 5 4 3 2 1 0
– – – CTC DTC SCR CCR DCR
Where:
The CTC bit (bit 4) resets both the CTCH and CTCL registers and the STC bit to 0.
The DTC bit (bit 3) resets both the DTCH and DTCL registers and the STD bit to 0.
The SCR bit (bit 2) resets both the SCRH and SCRL registers to 0.
The CCR bit (bit 1) resets both the CCRH and CCRL registers to 0.
The DCR bit (bit 0) resets both the DCRH and DCRL registers to 0.
offset register (OFR)
The OFR register (address = 73 hex) is used to store the calculated V
(OS)
of the bq26231. The OFR value can
be used to cancel the voltage offset between V
(SR1)
and V
(SR2)
. The up/down offset counter is centered at zero.
The actual offset is an 8-bit 2s complement value located in OFR.
The OFR locations are
TMP/CLR BITS
7 6 5 4 3 2 1 0
OFR7 OFR6 OFR5 OFR4 OFR3 OFR2 OFR1 OFR0
where OFR7 is
0 Discharge
1 Charge