Datasheet

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SLUS491 – JULY 2001
14
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APPLICATION INFORMATION
mode/wake-up enable register (continued)
The WOE 3–1 locations are
MODE/WOE BITS
7 6 5 4 3 2 1 0
– – – – WOE3 WOE2 WOE1 –
where WOE3–1 is determined by dividing 3.84 mV by the value in WOE.
NOTE:
Bit 0 of the MODE/WOE register is reserved and must remain 0.
Table 5. WOE Thresholds
WOE3–1 (hex) V
(WOE) (mV)
0 N/A
1 3.840
2 1.920
3 1.280
4 0.960
5 0.768
6 0.640
7 (default after POR) 0.549
temperature and clear register
The TMP/CLR register (address = 74 hex) is used to give the present temperature step between < 0°C and
> 60°C and clear the various count registers. The values of the TMP0–TMP2 (bits 5–7) denote the current
temperature step sense by the bq26231 as outlined in Table 3. The bq26231 temperature sense is trimmed
to ±2°C typical (±4°C maximum).
The TMP2–0 locations are
TMP/CLR BITS
7 6 5 4 3 2 1 0
TMP2 TMP1 TMP0 – – – – –
where TMP2–0 is the temperature step sensed by this bq26231.
The Clear bits (Bits 0–4) are used to reset the various bq26231 counters and STC and STD bits to zero. Writing
the bits to 1 resets the corresponding register to 0. The clear bit resets to 0, indicating a successful register reset.
Each clear bit is independent, so it is possible to clear the DCRH/DCRL registers without affecting the values
in any other bq26231 register. The high-byte and low-byte registers are both cleared when the corresponding
bit is written to 1.