Datasheet

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t
PDH
t
PDL
t
RSTL
t
RSTH
(c)bq26100TransmittedBitTiming
(a)ResetandPresenceTiming
(b)HostTransmittedBitTiming
t
LOW1
t
LOW0 SLOT
&t
t
SU
t
REC
t
RELEASE
t
REC
t
SLOT
t
RDV
t
LOWR
bq26100
SLUS696A – JUNE 2006 – REVISED FEBRUARY 2007
STANDARD SERIAL COMMUNICATION (SDQ) TIMING (continued)
over recommended operating temperature and supply voltage range (unless otherwise noted) (See Figure 1 )
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
SLOT
Host bit window 60 120 µ s
t
LOW1
Host sends 1 1 13 µ s
t
LOW0
Host sends 0 60 120 µ s
t
LOWR
Host read bit start 1 13 µ s
t
SLOT
bq26100 bit window 60 120 µ s
t
SU
bq26100 data setup 1 µ s
t
RDV
bq26100 data valid exactly 15 µ s
t
RELEASE
bq26100 data release 0 15 45 µ s
Figure 1. SDQ Timing Diagrams
The SDQ protocol requires a CRC calculation as part of the communication flow. The CRC, based on a
polynomial of x
8
+x
5
+x
4
+1, is computed to determine data integrity and its use varies in the protocol. The Memory
Function flows show what data is shifted through the CRC and when the value is transmitted from the slave.
Each data byte used in the CRC calculation is pushed through the CRC shift register from LSB to MSB. The
byte wide CRC computation is:
for (i = 0; i < 8; i++)
{
if (crc[0] ^ input[i])
crc = (crc >> 1) ^ 0x8C;
else
crc = crc >> 1;
}
Where did the magic number 0x8C come from? CRC polynomials are defined such that the highest order simply
shows the number of bits, so x
8
+x
5
+x
4
+1 defines an 8-bit value with a binary value of 00110001 (bits 0, 4, and 5
are 1 and all others are 0). Since the SDQ CRC is computed by shifting in the LSB, the polynomial must be
used in reverse bit order – binary 10001100 or hexadecimal 0x8C.
The CRC value is reset to 0 prior to the first byte being shifted through. The CRC is also reset when the CRC is
shifted out as part of the SDQ protocol.
3
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