Datasheet

bq24765

SLUS999 –NOVEMBER 2009

www.ti.com

DETAILED DESCRIPTION

SMBus INTERFACE

The bq24765 operates as a slave, receiving control inputs from the embedded controller host through the SMBus

interface.

BATTERY-CHARGER COMMANDS

The bq24765 supports five battery-charger commands that use either Write-Word or Read-Word protocols, as

summarized in Table 2. ManufacturerID() and DeviceID() can be used to identify the bq24765. On the bq24765,

the ManufacturerID() command always returns 0x0040 and the DeviceID() command always returns 0x0006.

Table 2. Battery Charger SMBus Registers

ADDRESS STATE VOLTAGE/CURRENT

0x14 ChargeCurrent() Read or Write 6-Bit Charge Current Setting 0x0000 0mA

0x15 ChargeVoltage() Read or Write 11-Bit Charge Voltage Setting 0x0000 0mV

0x3F InputCurrent() Read or Write 6-Bit Input Current Setting 0x0080 256mA (10mΩ RAC)

0xFE ManufacturerID() Read Only Manufacturer ID 0x0040 –

0xFF DeviceID() Read Only Device ID 0x0007 –

SMBus Interface

The bq24765 receives control inputs from the SMBus interface. The bq24765 uses a simplified subset of the

commands documented in System Management Bus Specification V1.1, which can be downloaded from

www.smbus.org. The bq24765 uses the SMBus Read-Word and Write-Word protocols (see Figure 28) to

communicate with the smart battery. The bq24765 performs only as an SMBus slave device with address

0b0001001_ (0x12) and does not initiate communication on the bus. In addition, the bq24765 has two

identification (ID) registers (0xFE): a 16-bit device ID register and a 16-bit manufacturer ID register (0xFF).

The data (SDA) and clock (SCL) pins have Schmitt-trigger inputs that can accommodate slow edges. Choose

pullup resistors (10kΩ) for SDA and SCL to achieve rise times according to the SMBus specifications.

Communication starts when the master signals a START condition, which is a high-to-low transition on SDA,

while SCL is high. When the master has finished communicating, the master issues a STOP condition, which is a

low-to-high transition on SDA, while SCL is high. The bus is then free for another transmission. Figure 29 and

Figure 30 show the timing diagram for signals on the SMBus interface. The address byte, command byte, and

data bytes are transmitted between the START and STOP conditions. The SDA state changes only while SCL is

low, except for the START and STOP conditions. Data is transmitted in 8-bit bytes and is sampled on the rising

edge of SCL. Nine clock cycles are required to transfer each byte in or out of the bq24765 because either the

master or the slave acknowledges the receipt of the correct byte during the ninth clock cycle.

Product Folder Link(s) :bq24765