Datasheet

Not Recommended for New Designs
bq24725
SLUS702A –JULY 2010–REVISED NOVEMBER 2010 www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
4.5 V ≤ V
VCC
≤ 24 V, 0°C ≤ T
J
≤ 125°C, typical values are at T
A
= 25°C, with respect to GND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ACFET GATE DRIVER (ACDRV)
I
ACFET
ACDRV charge pump current limit 40 60 μA
V
ACFET
Gate drive voltage on ACFET V
ACDRV
–V
CMSRC
when V
VCC
> UVLO 5.5 6.1 6.5 V
Minimum load resistance between ACDRV
R
ACDRV_LOAD
500 kΩ
and CMSRC
R
ACDRV_OFF
ACDRV turn-off resistance I = 30µA 5 6.2 7.4 kΩ
ACDRV Turn-Off when Vgs voltage is low
V
ACFET_LOW
5.9 V
(Specified by design)
PWM HIGH SIDE DRIVER (HIDRV)
High side driver (HSD) turn-on resistance V
BTST
– V
PH
= 5.5 V, I = 10mA 12 20 Ω
R
DS(on)
High side driver turn-off resistance V
BTST
– V
PH
= 5.5 V, I = 10mA 0.65 1.3 Ω
Bootstrap refresh comparator threshold V
BTST
– V
PH
when low side refresh pulse is requested
V
BTST_REFRESH
3.85 4.3 4.7 V
voltage
PWM LOW SIDE DRIVER (LODRV)
Low side driver (LSD) turn-on resistance V
REGN
= 6 V, I = 10 mA 15 25 Ω
R
DS(on)
Low side driver turn-off resistance V
REGN
= 6 V, I = 10 mA 0.9 1.4 Ω
PWM DRIVER TIMING
t
LOW_HIGH
Driver dead time from low side to high side 20 ns
t
HIGH_LOW
Driver dead time from high side to low side 20 ns
INTERNAL SOFT START
I
STEP
Soft start current step 64 mA
In CCM mode 10mΩ current sensing resistor
t
STEP
Soft start current step time 240 μs
SMBus TIMING CHARACTERISTICS
t
R
SCLK/SDATA rise time 1 μs
t
F
SCLK/SDATA fall time 300 ns
t
W(H)
SCLK pulse width high 4 50 μs
t
W(L)
SCLK Pulse Width Low 4.7 μs
t
SU(STA)
Setup time for START condition 4.7 μs
t
H(STA)
START condition hold time after which first clock pulse is generated 4 μs
t
SU(DAT)
Data setup time 250 ns
t
H(DAT)
Data hold time 300 ns
t
SU(STOP)
Setup time for STOP condition 4 µs
t
(BUF)
Bus free time between START and STOP condition 4.7 μs
F
S(CL)
Clock Frequency 10 100 kHz
HOST COMMUNICATION FAILURE
t
timeout
SMBus bus release timeout
(2)
25 35 ms
t
BOOT
Deglitch for watchdog reset signal 10 ms
Watchdog timeout period, ChargeOption()
35 44 53 s
bit [14:13] = 01
(3)
Watchdog timeout period, ChargeOption()
t
WDI
70 88 105 s
bit [14:13] = 10
(3)
Watchdog timeout period, ChargeOption()
140 175 210 s
bit [14:13] = 11
(3)
(Default)
(2) Devices participating in a transfer will timeout when any clock low exceeds the 25ms minimum timeout period. Devices that have
detected a timeout condition must reset the communication no later than the 35ms maximum timeout period. Both a master and a slave
must adhere to the maximum value specified as it incorporates the cumulative stretch limit for both a master (10ms) and a slave (25ms).
(3) User can adjust threshold via SMBus ChargeOption() REG0x12.
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