Datasheet

bq24725A
www.ti.com SLUSAL0 –SEPTEMBER 2011
ELECTRICAL CHARACTERISTICS (continued)
4.5 V ≤ V
VCC
≤ 24 V, 0°C ≤ T
J
≤ 125°C, typical values are at T
A
= 25°C, with respect to GND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT (ACDET, ILIM)
I
IN_ LEAK
Input bias current V = 7 V –1 1 μA
PWM OSCILLATOR
F
SW
PWM switching frequency ChargeOption () bit [9] = 0 (Default) 600 750 900 kHz
F
SW+
PWM increase frequency ChargeOption() bit [10:9] = 11 665 885 1100 kHz
F
SW–
PWM decrease frequency ChargeOption() bit [10:9] = 01 465 615 765 kHz
BATFET GATE DRIVER (BATDRV)
I
BATFET
BATDRV charge pump current limit 40 60 µA
V
BATFET
Gate drive voltage on BATFET V
BATDRV
- V
SRN
when V
SRN
> UVLO 5.5 6.1 6.5 V
Minimum load resistance between
R
BATDRV_LOAD
500 kΩ
BATDRV and SRN
R
BATDRV_OFF
BATDRV turn-off resistance I = 30 µA 5 6.2 7.4 kΩ
ACFET GATE DRIVER (ACDRV)
I
ACFET
ACDRV charge pump current limit 40 60 μA
V
ACFET
Gate drive voltage on ACFET V
ACDRV
–V
CMSRC
when V
VCC
> UVLO 5.5 6.1 6.5 V
Minimum load resistance between ACDRV
R
ACDRV_LOAD
500 kΩ
and CMSRC
R
ACDRV_OFF
ACDRV turn-off resistance I = 30 µA 5 6.2 7.4 kΩ
ACDRV Turn-Off when Vgs voltage is low
V
ACFET_LOW
5.9 V
(Specified by design)
PWM HIGH SIDE DRIVER (HIDRV)
R
DS_HI_ON
High side driver turn-on resistance V
BTST
– V
PH
= 5.5 V, I = 10 mA 6 10 Ω
R
DS_HI_OFF
High side driver turn-off resistance V
BTST
– V
PH
= 5.5 V, I = 10 mA 0.65 1.3 Ω
Bootstrap refresh comparator threshold V
BTST
– V
PH
when low side refresh pulse is requested
V
BTST_REFRESH
3.85 4.3 4.7 V
voltage
PWM LOW SIDE DRIVER (LODRV)
R
DS_LO_ON
Low side driver turn-on resistance V
REGN
= 6 V, I = 10 mA 7.5 12 Ω
R
DS_LO_OFF
Low side driver turn-off resistance V
REGN
= 6 V, I = 10 mA 0.9 1.4 Ω
PWM DRIVER TIMING
t
LOW_HIGH
Driver dead time from low side to high side 20 ns
t
HIGH_LOW
Driver dead time from high side to low side 20 ns
INTERNAL SOFT START
I
STEP
Soft start current step 64 mA
In CCM mode 10mΩ current sensing resistor
t
STEP
Soft start current step time 240 μs
SMBus TIMING CHARACTERISTICS
t
R
SCLK/SDATA rise time 1 μs
t
F
SCLK/SDATA fall time 300 ns
t
W(H)
SCLK pulse width high 4 50 μs
t
W(L)
SCLK Pulse Width Low 4.7 μs
t
SU(STA)
Setup time for START condition 4.7 μs
t
H(STA)
START condition hold time after which first clock pulse is generated 4 μs
t
SU(DAT)
Data setup time 250 ns
t
H(DAT)
Data hold time 300 ns
t
SU(STOP)
Setup time for STOP condition 4 µs
t
(BUF)
Bus free time between START and STOP condition 4.7 μs
F
S(CL)
Clock Frequency 10 100 kHz
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