Datasheet

S
SLAVE
ADDRESS
W ACK
COMMAND
BYTE
ACK
LOW DATA
BYTE
ACK
HIGH DATA
BYTE
ACK P
7 BITS 1b 1b 8 BITS 1b 8 BITS 1b 8 BITS 1b
MSB LSB 0 0 MSB LSB 0 MSB LSB 0 MSB LSB 0
a) Write-Word Format
S
SLAVE
ADDRESS
W ACK
COMMAND
BYTE
ACK S
SLAVE
ADDRESS
R ACK
LOW DATA
BYTE
ACK
HIGH DATA
BYTE
NACK P
7 BITS 1b 1b 8 BITS 1b 7 BITS 1b 1b 8 BITS 1b 8 BITS 1b
MSB LSB 0 0 MSB LSB 0 MSB LSB 1 0 MSB LSB 0 MSB LSB 1
Preset to 0b0001001 DeviceID() = 0xFFH Preset to D7 D0 D15 D8
ManufactureID() = 0xFEH 0b0001001
ChargeCurrent() = 0x14H
ChargeVoltage() = 0x15H
InputCurrent() = 0x3FH
ChargeOption() = 0x12H LEGEND:
S = START CONDITION OR REPEATED START CONDITION P = STOP CONDITION
ACK = ACKNOWLEDGE (LOGIC-LOW) NACK = NOT ACKNOWLEDGE (LOGIC-HIGH)
W = WRITE BIT (LOGIC-LOW) R = READ BIT (LOGIC-HIGH)
b) Read-Word Format
MASTER TO SLAVE
SLAVE TO MASTER
Preset to 0b0001001
ChargeOption() = 0x12H
D7
D0 D15 D8
ChargeCurrent() = 0x14H
ChargeVoltage() = 0x15H
InputCurrent() = 0x3FH
bq24725A
SLUSAL0 –SEPTEMBER 2011 www.ti.com
DETAILED DESCRIPTION
SMBus Interface
The bq24725A operates as a slave, receiving control inputs from the embedded controller host through the
SMBus interface. The bq24725A uses a simplified subset of the commands documented in System Management
Bus Specification V1.1, which can be downloaded from www.smbus.org. The bq24725A uses the SMBus
Read-Word and Write-Word protocols (see Figure 16) to communicate with the smart battery. The bq24725A
performs only as a SMBus slave device with address 0b00010010 (0x12H) and does not initiate communication
on the bus. In addition, the bq24725A has two identification registers a 16-bit device ID register (0xFFH) and a
16-bit manufacturer ID register (0xFEH).
SMBus communication is enabled with the following conditions:
• V
VCC
is above UVLO;
• V
ACDET
is above 0.6V;
The data (SDA) and clock (SCL) pins have Schmitt-trigger inputs that can accommodate slow edges. Choose
pull-up resistors (10kΩ) for SDA and SCL to achieve rise times according to the SMBus specifications.
Communication starts when the master signals a START condition, which is a high-to-low transition on SDA,
while SCL is high. When the master has finished communicating, the master issues a STOP condition, which is a
low-to-high transition on SDA, while SCL is high. The bus is then free for another transmission. Figure 17 and
Figure 18 show the timing diagram for signals on the SMBus interface. The address byte, command byte, and
data bytes are transmitted between the START and STOP conditions. The SDA state changes only while SCL is
low, except for the START and STOP conditions. Data is transmitted in 8-bit bytes and is sampled on the rising
edge of SCL. Nine clock cycles are required to transfer each byte in or out of the bq24725A because either the
master or the slave acknowledges the receipt of the correct byte during the ninth clock cycle. The bq24725A
supports the charger commands as described in Table 2.
Figure 16. SMBus Write-Word and Read-Word Protocols
16 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s) :bq24725A