Datasheet

bq24640
www.ti.com SLUSA44 –MARCH 2010
PIN FUNCTIONS (continued)
PIN
TYPE
(1)
PIN DESCRIPTION
NO. NAME
14 PH P Switching node, charge current output inductor connection. Connect the 0.1-mF bootstrap capacitor from PH
to BTST.
15 HIDRV O PWM high side driver output. Connect to the gate of the high side N-channel power MOSFET with a short
trace.
16 BTST P PWM high side driver positive supply. Connect the 0.1-mF bootstrap capacitor from PH to BTST.
PowerPad Exposed pad beneath the IC. Always solder Power Pad to the board, and have vias on the Power Pad plane
star-connecting to GND and ground plane for high-current power converter. It also serves as a thermal pad to
dissipate the heat.
ORDERING INFORMATION
ODERING NUMBER
PART NUMBER IC MARKING PACKAGE QUANTITY
(Tape and Reel)
bq24640RVAR 3000
bq24640 OGA 16-PIN 3.5×3.5 mm QFN
bq24640RVAT 250
THERMAL INFORMATION
bq24640
THERMAL METRIC
(1)
(RVA) UNITS
(QFN-16) PINS
q
JA
Junction-to-ambient thermal resistance
(2)
43.8
q
JC(top)
Junction-to-case(top) thermal resistance
(3)
81
q
JB
Junction-to-board thermal resistance
(4)
16
°C/W
y
JT
Junction-to-top characterization parameter
(5)
0.6
y
JB
Junction-to-board characterization parameter
(6)
15.77
q
JC(bottom)
Junction-to-case(bottom) thermal resistance
(7)
4
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case(top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard
test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, y
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining q
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, y
JB
estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining q
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case(bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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