Datasheet

apacitor
Cff
22 pF
VCC
REGN
BTST
HIDRV
PH
LODRV
GND
SRP
SRN
VFB
VREF
CE
ISET
TS
STAT
PG
Q5
SiS412DN
L: 6.8 µH
C13
10 mF
RSR
10m W
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C 8
10 mF
Q4
SiS412DN
C 2
2.2 mF
Adapter
C12
10mF
C1 1: 0.1 µF
C5:1 mF
C 4
1mF
Super C
C 7:1 mF
R2
300 kW
R1
105 kW
R7
100 kW
R8
22.1 kW
R9
9.31 kW
R10
430 kW
Temp
S ensing
10k
(SEMITEC
103AT - 2)
R1 3 :10 kW
R1 4:10 kW
Adapter
R 11
2W
R6: 10 W
D2
MBRS540T3
R 5: 100 W
C1
0.1 m F
PwrPad
D1
BAT54
C 9
10 mF
C 6
0. 1 mF
C10
0.1 m F
´
ISET
CHG
SR
V
I =
20 R
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SLUSA44 –MARCH 2010 www.ti.com
TYPICAL APPLICATION
V
IN
= 19 V, V
OUT
= 8.1 V, I
charge
= 3 A, Temperature range 0–45°C
Figure 1. Typical System Schematic
PIN FUNCTIONS
PIN
TYPE
(1)
PIN DESCRIPTION
NO. NAME
1 VCC P IC power positive supply. Connect through a 10-Ω resistor to the cathode of input diode. Place a 1-mF ceramic
capacitor from VCC to GND and place it as close as possible to IC to filter out the noise.
2 CE I Charge enable, active HIGH logic input. HI enables charge, and LO disables charge. Connect to pull-up rail
with 10-kΩ resistor. It has an internal 1-MΩ pull-down resistor.
3 STAT O Open drain charge status output to indicate various charger operation. Connect to the pull-up rail through the
LED and 10-kΩ. (See Table 3)
4 TS I Temperature qualification voltage input for negative temperature coefficient thermistor. Program the hot and
cold temperature window with a resistor divider from VREF to TS to GND. Recommend SEMITEC 103AT-2
10-kΩ thermister.
5 PG O Open drain active-low adapter status output. Connect to pull-up rail through LED and 10 kΩ resistor. The LED
turns on when a valid is detected, and off in the sleep mode.
6 VREF P 3.3V reference voltage output. Place a 1-mF ceramic capacitor from VREF to GND pin close to the IC. This
voltage could be used for programming charge current regulation on ISET and for thermal threshold on TS. It
can be used as the pull up rail of STAT, and PG.
7 ISET I Charge current set point. The voltage is set through a voltage divider from VREF to ISET and to GND.
8 VFB I Charge voltage analog feedback adjustment. Connect a resistor divider from output to VFB to GND to adjust
the output voltage. The internal regulation limit is 2.1V.
9 SRN I Charge current sense resistor, negative input. A 0.1-mF ceramic capacitor is placed from SRN to SRP to
provide differential-mode filtering. An optional 0.1-mF ceramic capacitor is placed from SRN pin to GND for
common-mode filtering.
10 SRP P/I Charge current sense resistor, positive input. A 0.1-mF ceramic capacitor is placed from SRN to SRP to
provide differential-mode filtering. A 0.1-mF ceramic capacitor is placed from SRP pin to GND for
common-mode filtering.
11 GND P Low-current sensitive analog/digital ground. On PCB layout, connect with PowerPad underneath the IC.
12 REGN P PWM low side driver positive 6V supply output. Connect a 1-mF ceramic capacitor from REGN to GND pin
close to the IC. Use for low side driver and high-side driver bootstrap voltage by small signal Schottky diode
from REGN to BTST.
13 LODRV O PWM low side driver output. Connect to the gate of the low side N-channel power MOSFET with a short trace.
(1) P - Power, I - Input, O - Output
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