Datasheet

VCC
BTST
HIDRV
PH
REGN
LODRV
GND
TS
CE
VREG
SRP
6V LDO
V(SRP-SRN)
COMP
ERROR
AMPLIFIER
20uA
1V
SRN
STATE
MACHINE
LOGIC
VCC
PH
4V
+
_
BTST
REFRESH
CE
145 degC
IC Tj
TSHUT
SRN+100mV
VCC
SLEEP
LEVEL
SHIFTER
+
-
+
-
+
-
+
-
+
-
V(SRP-SRN)
CHG_OCP
+
-
160% X ISET
SYNCH
SRP-SRN
ISET
5 mV
20X
OUT_OVP
+
-
104% X VREG
LTF
+
-
HTF
VREF
TCO
+
-
+
-
SUSPEND
VCC
ACOV
+
-
V
ACOV
CE
VREF
STAT
STAT
3.3V
LDO
VCC
bq24640
+
-
+
-
UVLO
V
UVLO
VCC
SLEEP
UVLO
PWM
CONTROL
LOGIC
+
-
PWM
+
-
+
-
+
-
PG
+
-
CHARGE
20uA
CHARGE
8mA
OUT_OVP
VOLTAGE
REFERENCE
VREF
PG
1M
FBO
EAO
EAI
VFB
VFB
bq24640
www.ti.com SLUSA44 –MARCH 2010
BLOCK DIAGRAM
Figure 9. Functional Block Diagram
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