Datasheet

VREF IN VREF VREF
ICLOSS ICLOSS _ driver VREF Quiescent
P (V V ) I
P P P P
= - ×
= + +
R1
2 W
C1
2.2 mF
D1
C2
0.1-1 mF
R2
4.7 -30W
Adapter
connector
VCCpin
(2010)
(1206)
bq24620
SLUS893A –MARCH 2010– REVISED OCTOBER 2011 www.ti.com
(22)
Input Filter Design
During adapter hot plug-in, the parasitic inductance and input capacitor from the adapter cable form a
second-order system. The voltage spike at the VCC pin may be beyond the IC maximum voltage rating and
damage the IC. The input filter must be carefully designed and tested to prevent an overvoltage event on VCC
pin.
There are several methods to damping or limiting the overvoltage spike during adapter hot plug-in. An electrolytic
capacitor with high ESR as an input capacitor can damp the overvoltage spike well below the IC maximum
pin-voltage rating. A high-current-capability TVS Zener diode can also limit the overvoltage level to an IC-safe
level. However, these two solutions may not have low cost or small size.
A cost-effective and small-size solution is shown in Figure 17. R1 and C1 comprise a damping RC network to
damp the hot plug-in oscillation. As a result, the overvoltage spike is limited to a safe level. D1 is used for
reverse voltage protection for the VCC pin (it can be the input Schottky diode or the body diode of the input
ACFET). C2 is a VCC pin-decoupling capacitor, and it should be placed as close as possible to the VCC pin. R2
and C2 form a damping RC network to further protect the IC from high-dv/dt and high-voltage spikes. The C2
value should be less than the C1 value so R1 can be dominant over the ESR of C1 to get enough damping effect
for hot plug-in. R1 and R2 packages must be sized to handle the inrush-current power loss according to the
resistor manufacturer’s data sheet. The filter component values always must be verified with the real application,
and minor adjustments may be needed to fit in the real application circuit.
Figure 17. Input Filter
PCB Layout
The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the
components to minimize the high-frequency current-path loop (see Figure 18) is important to prevent electrical
and magnetic field radiation and high-frequency resonant problems. Here is a PCB layout priority list for proper
layout. Layout of the PCB according to this specific order is essential.
1. Place the input capacitor as close as possible to the switching MOSFET supply and ground connections, and
use the shortest possible copper trace connection. These parts should be placed on the same layer of the
PCB instead of on different layers, using vias to make this connection.
2. The IC should be placed close to the switching MOSFET gate terminals, keeping the gate-drive signal traces
short for a clean MOSFET drive. The IC can be placed on the other side of the PCB from the switching
MOSFETs.
3. Place the inductor input terminal as close as possible to switching MOSFET output terminal. Minimize the
copper area of this trace to lower electrical and magnetic field radiation, but make the trace wide enough to
carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic
capacitance from this area to any other trace or plane.
4. The charging-current-sensing resistor should be placed right next to the inductor output. Route the sense
leads connected across the sensing resistor back to the IC in same layer, close to each other (minimize loop
area), and do not route the sense leads through a high-current path (see Figure 19 for Kelvin connection for
best current accuracy). Place the decoupling capacitor on these traces next to the IC.
5. Place the output capacitor next to the sensing-resistor output and ground.
6. The output-capacitor ground connections must be tied to the same copper that connects to the
input-capacitor ground before connecting to system ground.
7. Route the analog ground separately from the power ground and use a single ground connection to tie the
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