Datasheet

D
E
TI YMLLLLS
bq24278
0-Pin A 1 Marker, TI-TI Letters, YM- Year Month Date Code ,
LLLL-Lot Trace Code , S-Assembly Site Code
CHIP SCALE PACKAGING DIMENSIONS
The bq 2427x devices are available in a 49-bump chip scale package (YFF, NanoFree
TM
). The package dimensions are :
D – 2.78mm ± 0.05mm
E – 2.78mm ± 0.05mm
GNDGNDGNDIN
BYPBYPBYPPMID
SWSWSWSW
PGN
D
PGN
D
PGN
D
SW
DRV_
S
PGN
D
BOO
T
/CE
IN
PMID
PGN
D
VDP
M
DRV_
S
1 2 3 4 5
A
B
C
D
E
IN
SW
CD
PMID
PGN
D
6
BGATE DRVSYSSYS /PG
F
SYS
IN
SW
ILIM
PMID
PGN
D
SYS
TS ISETBATBAT /CHGBATBAT
G
7
bq24278
www.ti.com SLUSB04 –JUNE 2012
also recommended to put vias inside the PGND pads for the IC, if possible. A star ground design approach is
typically used to keep circuit block currents isolated (high-power/low-power small-signal) which reduces noise-
coupling and ground-bounce issues. A single ground plane for this design gives good results. With this small
layout and a single ground plane, there is no ground-bounce issue, and having the components segregated
minimizes coupling between signals.
• The high-current charge paths into IN, BAT, SYS and from the SW pins must be sized appropriately for the
maximum charge current in order to avoid voltage drops in these traces. The PGND pins should be
connected to the ground plane to return current through the internal low-side FET.
• For high-current applications, the balls for the power paths should be connected to as much copper in the
board as possible. This allows better thermal performance as the board pulls heat away from the IC.
PACKAGE SUMMARY
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