Datasheet

IN
SW
ILIM
SW
SW
BOOT
ISET
SYS
SYS
PGND
PMID
GND
PGND
BAT
(YFF Package)
SW
BOOT
ILIM
ISET
GND
BYP
PMID
PGND
SYS
SYS
BAT
(RGE Package)
bq24278
SLUSB04 –JUNE 2012 www.ti.com
PCB Layout Guidelines
It is important to pay special attention to the PCB layout. Figure 7 provides a sample layout for the high current
paths of the bq24278.
Figure 7. Recommended bq24278 PCB Layout for RGE Device
Figure 8. Recommended bq24278 PCB Layout for YFF Device
The following provides some guidelines:
• To obtain optimal performance, the power input capacitors, connected from the PMID input to PGND, must be
placed as close as possible to the bq24278
• Place 4.7µF input capacitor as close to PMID pin and PGND pin as possible to make high frequency current
loop area as small as possible. Place 1µF input capacitor GNDs as close to the respective PMID cap GND
and PGND pins as possible to minimize the ground difference between the input and PMID.
• The local bypass capacitor from SYS to GND should be connected between the SYS pin and PGND of the
IC. The intent is to minimize the current path loop area from the SW pin through the LC filter and back to the
PGND pin.
• Place ISET resistor very close to the ISET pin.
• Place ILIM resistor very close to the ILIIM pin.
• Place all decoupling capacitor close to their respective IC pin and as close as to PGND (do not place
components such that routing interrupts power stage currents). All small control signals should be routed
away from the high current paths.
• The PCB should have a ground plane (return) connected directly to the return of all components through vias
(two vias per capacitor for power-stage capacitors, one via per capacitor for small-signal components). It is
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