Datasheet

RLO 0.383 RHI
RWARM
RLO RLO 0.383 R HI 0.383
´ ´
=
- ´ - ´
RLO 0.564 RHI
RCOOL
RLO RLO 0.564 RHI 0.564
´ ´
=
- ´ - ´
DRV
COLD
V
1
V
RHI
1 1
RLO RCOLD
-
=
+
DRV
COLD HOT
DRV DRV
HOT COLD
1 1
V RCOLD RHOT
V V
RLO
V V
RHOT 1 RCOLD 1
V V
é ù
´ ´ ´ -
ê ú
ë û
=
é ù é ù
´ - - ´ -
ê ú ê ú
ë û ë û
bq24278
SLUSB04 –JUNE 2012 www.ti.com
(3)
(4)
Where:
V
COLD
= 0.60 × V
DRV
V
HOT
= 0.30 × V
DRV
Where RHOT is the NTC resistance at the hot temperature and RCOLD is the NTC resistance at cold
temperature.
The WARM and COOL thresholds are not independently programmable. The COOL and WARM NTC
resistances for a selected resistor divider are calculated using the following equations:
(5)
(6)
Thermal Regulation and Protection
During the charging process, to prevent the IC from overheating, bq24278 monitor the junction temperature, T
J
,
of the die and begins to taper down the charge current once T
J
reaches the thermal regulation threshold, T
CF
.
The charge current is reduced to zero when the junction temperature increases about 10°C above TCF. Once
the charge current is reduced, the system current is reduced while the battery supplements the load to supply the
system. This may cause a thermal shutdown of the bq24278 if the die temperature rises too high. At any state, if
T
J
exceeds T
SHTDWN
, bq24278 suspends charging and disables the buck converter. During thermal shutdown
mode, PWM is turned off, and the timer is reset. The charging cycle resets when T
J
falls below T
SHTDWN
by
approximately 10°C.
Input Voltage Protection in Charge Mode
Sleep Mode
The bq24278 enters the low-power sleep mode if the voltage on VIN falls below sleep-mode entry threshold,
V
BAT
+V
SLP
, and V
VBUS
is higher than the undervoltage lockout threshold, V
UVLO
. This feature prevents draining
the battery during the absence of V
IN
. When V
IN
< V
BAT
+ V
SLP
, the bq24278 turns off the PWM converter, and
turns the battery FET and BGATE on. Once V
IN
> V
BAT
+ V
SLP
, the device initiates a new charge cycle.
Input Voltage Based DPM
During normal charging process, if the input power source is not able to support the programmed or default
charging current, the supply voltage decreases. Once the supply drops to V
IN_DPM
(set by VDPM), the input
current limit is reduced down to prevent the further drop of the supply. This feature ensures IC compatibility with
adapters with different current capabilities without a hardware change. Figure 6 shows the V
IN-DPM
behavior to a
current limited source. In this figure the input source has a 750mA current limit and the charging is set to 750mA.
The SYS load is then increased to 1.2A.
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