Datasheet

bq24272
www.ti.com SLUSB09 –JUNE 2012
PIN FUNCTIONS
PIN NO. bq24272
PIN NAME I/O DESCRIPTION
YFF RGE
Input power supply. IN is connected to the external DC supply (AC adapter or alternate power source). Bypass
IN A1–A4 21 I
IN to PGND with at least a 1μF ceramic capacitor.
Reverse Blocking MOSFET and High Side MOSFET Connection Point for High Power Input. Bypass PMID to
PMID B1–B4 20 O GND with at least a 4.7μF ceramic capacitor. Use caution when connecting an external load to PMID. The
PMID output is not current limited. Any short on PMID will result in damage to the IC.
Bypass for internal circuits. Bypass BYP to GND with at least 0.1µF of capacitance. Do not connect any
BYP B5–B7 23 O
external load to BYP.
SW C1–C7 18 O Inductor Connection. Connect to the switched side of the external inductor.
A5–A7,
AGND 5, 22 — Ground terminal.
E1, G7
PGND D1–D7 15, 16, 17 — Ground terminal. Connect to the thermal pad (for QFN only) and the ground plane of the circuit.
N.C. E2, E3 1, 2 I No connection. Leave N.C. unconnected.
IC Hardware Disable Input. Drive CD high to place the bq24272 in High-Z mode. Drive CD low for normal
CD E4 24 I
operation.
SDA E5 4 I/O I2C Interface Data. Connect SDA to the logic rail through a 10kΩ resistor.
SCL E6 3 I I2C Interface Clock. Connect SCL to the logic rail through a 10kΩ resistor.
High Side MOSFET Gate Driver Supply. Connect a 0.01µF ceramic capacitor (voltage rating > 10V) from
BOOT E7 19 I
BOOT to SW to supply the gate drive for the high side MOSFETs.
System Voltage Sense and Charger FET Connection. Connect SYS to the system output at the output bulk
SYS F1–F4 13, 14 I
capacitors. Bypass SYS locally with 10μF.
External Discharge MOSFET Gate Connection. BGATE drives an external P-Channel MOSFET to provide a
BGATE F5 10 O very low resistance discharge path. Connect BGATE to the gate of the external MOSFET. BGATE is low during
supplement mode and when no input is connected.
Status Output. INT is an open-drain output that signals charging status and fault interrupts. INT pulls low during
charging. INT is high impedance when charging is complete or the charger is disabled. When a fault occurs, a
INT F6 7 O
128μs pulse is sent out as an interrupt for the host. INT is enabled /disabled using the EN_STAT bit in the
control register. Connect INT to a logic rail through a 100kΩ resistor to communicate with the host processor.
Gate Drive Supply. DRV is the bias supply for the gate drive of the internal MOSFETs. Bypass DRV to PGND
DRV F7 6 O with a 1μF ceramic capacitor. DRV may be used to drive external loads up to 10mA. DRV is active whenever
the input is connected and
VIN
> V
UVLO
and V
SUPPLY
> (V
BAT
+ V
SLP
)
Battery Connection. Connect to the positive terminal of the battery. Additionally, bypass BAT to GND with a
BAT G1–G4 11, 12 I/O
1μF capacitor.
Battery Pack NTC Monitor. Connect TS to the center tap of a resistor divider from DRV to GND. The NTC is
connected from TS to GND. The TS function provides 4 thresholds for JEITA compatibility. TS faults are
TS G5 9 I
reported by the I
2
C interface. See the NTC Monitor section for more details on operation and selecting the
resistor values.
Status Output. STAT is an open-drain output that signals charging status and fault interrupts. STAT pulls low
during charging. STAT is high impedance when charging is complete or the charger is disabled. When a fault
STAT G6 8 O occurs, a 128μs pulse is sent out as an interrupt for the host. STAT is enabled /disabled using the EN_STAT
bit in the control register. Connect STAT to a logic rail using an LED for visual indication or through a 10kΩ
resistor to communicate with the host processor.
There is an internal electrical connection between the exposed thermal pad and the VSS pin of the device. The
Thermal
— Pad — thermal pad must be connected to the same potential as the VSS pin on the printed circuit board. Do not use
PAD
the thermal pad as the primary ground input for the device. VSS pin must be connected to ground at all times.
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