Datasheet

bq24272
SLUSB09 –JUNE 2012 www.ti.com
HZ_MODE Bit (High Impedance Mode Enable)
The HZ_MODE bit in the control register (0x02h) is used to disable or enable the high impedance mode. A low
logic level (0) on this bit enables the IC and a high logic level (1) puts the IC in a low quiescent current state
called high impedance mode. When in high impedance mode, the converter is off and the battery FET and
BGATE are on. The load on SYS is supplied by the battery.
Control/Battery Voltage Register (READ/WRITE)
Memory location: 03, Reset state: 0001 0100
BIT NAME Read/Write FUNCTION
B7(MSB) V
BREG5
Read/Write Battery Regulation Voltage: 640mV (default 0)
B6 V
BREG4
Read/Write Battery Regulation Voltage: 320mV (default 0)
B5 V
BREG3
Read/Write Battery Regulation Voltage: 160mV (default 0)
B4 V
BREG2
Read/Write Battery Regulation Voltage: 80mV (default 1)
B3 V
BREG1
Read/Write Battery Regulation Voltage: 40mV (default 0)
B2 V
BREG0
Read/Write Battery Regulation Voltage: 20mV (default 1)
B1 I
INLIMIT_IN
Read/Write Input Limit for IN input
0 – 1.5A
1 – 2.5A (default 0)
B0(LSB) NA Read/Write NA
• Charge voltage range is 3.5V–4.44V with the offset of 3.5V and step of 20mV (default 3.6V).
Vender/Part/Revision Register (READ only)
Memory location: 04, Reset state: 0100 0000
BIT NAME Read/Write FUNCTION
B7(MSB) Vender2 Read only Vender Code: bit 2 (default 0)
B6 Vender1 Read only Vender Code: bit 1 (default 1)
B5 Vender0 Read only Vender Code: bit 0 (default 0)
B4 PN1 Read only For I
2
C Address 6Bh:
00: bq24272
B3 PN0 Read only
01 – 11: Future product spins
B2 Revision2 Read only 000: Revision 1.0
001:Revision 1.1
B1 Revision1 Read only
010: Revision 2.0
B0(LSB) Revision0 Read only
011: Revision 2.1
100: Revision 2.2
101: Revision 2.3
110-111: Future Revisions
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