Datasheet

DISABLE
TEMP
PACK+
PACK–
+
+
V
DRV
TS COLD
TS HOT
TS
bq24272
RHI
RLO
V
DRV
bq24272
SLUSB09 –JUNE 2012 www.ti.com
Where RHOT is the NTC resistance at the hot temperature and RCOLD is the NTC resistance at cold
temperature.
Figure 6. TS Circuit
If the TS function is not used, connect TS to DRV directly to disable the feature. Additionally, the TS function can
be disabled in the I
2
C by writing to the EN_TS bit. When the TS is disabled, the status registers always read
“Normal”.
Thermal Regulation and Protection
During the charging process, to prevent chip overheating, bq24272 monitors the junction temperature, T
J
, of the
die and begins to taper down the charge current once T
J
reaches the thermal regulation threshold, T
REG
. The
charge current is reduced to zero when the junction temperature increases about 10°C above T
REG
. Once the
charge current is reduced, the system current is reduced while the battery supplements the load to supply the
system. This may cause a thermal shutdown of the bq24272 if the die temperature rises too high. At any state, if
T
J
exceeds T
SHTDWN
, bq24272 suspends charging and disables the buck converter. During thermal shutdown
mode, the PWM is turned off, all timers are suspended, and a single 128μs pulse is sent on the STAT and INT
outputs and the STATx and FAULT_x bits of the status registers are updated in the I
2
C. A new charging cycle
begins when T
J
falls below T
SHTDWN
by approximately 10°C.
Input Voltage Protection in Charge Mode
Sleep Mode
The bq24272 enters the low-power sleep mode if the voltage on V
IN
falls below sleep-mode entry threshold,
V
BAT
+V
SLP
, and V
VBUS
is higher than the undervoltage lockout threshold, V
UVLO
. This feature prevents draining
the battery during the absence of V
IN
. When V
IN
< V
BAT
+ V
SLP
, the bq24272 turns off the PWM converter, turns
the battery FET on and drives BGATE to GND, sends a single 128μs pulse on the STAT and INT outputs and
updates the STATx and FAULT_x bits in the status registers. Once V
IN
> V
BAT
+ V
SLP
, the STATx and FAULT_x
bits are cleared and the device initiates a new charge cycle.
Input Voltage Based DPM
During normal charging process, if the input power source is not able to support the programmed or default
charging current, the supply voltage will decease. Once the supply drops to V
IN_DPM
(default 4.2V), the input
current limit is reduced down to prevent further supply droop. When the IC enters this mode, the charge current
is lower than the set value and the DPM_STATUS bit is set (Bit 5 in Register 05H). This feature ensures IC
compatibility with adapters with different current capabilities without a hardware change. Figure 7 shows the V
IN-
DPM
behavior to a current limited source. In this figure the input source has a 750mA current limit and the
charging is set to 750mA. The SYS load is then increased to 1.2A.
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