Datasheet

1
7
Slave Address
S
1
1
ACK
8
Reg Addr
ACK
1
ACK
1
1
P
7
0
1
Data
NCK
8
Slave Address
1
1
1
S
1
7
Slave Address
S
1
1
ACK
8
Reg Addr
ACK
1
Data Addr
ACK
1
1
P
8
0
START
SCL
SDA
S
1-7
8 9
ACK
1-7
8 9
ACK
1-7
8 9
STOP
P
ADDRESS
R/W
DATA ACKDATA
SCL
SDA
START or
Repeated
START
S or Sr 1
2
7 8 9
MSB
ACK
Acknowledgement
signal from slave
1
2
8 9
ACK
Acknowledgement
signal from receiver
STOP or
Repeated
START
P or Sr
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bq24192I, bq24193
www.ti.com SLUSAW5A –JANUARY 2012–REVISED OCTOBER 2012
Byte Format
Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is
unrestricted. Each byte has to be followed by an Acknowledge bit. Data is transferred with the Most Significant
Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has performed some
other function, it can hold the clock line SCL low to force the master into a wait state (clock stretching). Data
transfer then continues when the slave is ready for another byte of data and release the clock line SCL.
Figure 35. Data Transfer on the I
2
C Bus
Acknowledge (ACK) and Not Acknowledge (NACK)
The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter
that the byte was successfully received and another byte may be sent. All clock pulses, including the
acknowledge 9
th
clock pulse, are generated by the master.
The transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line
LOW and it remains stable LOW during the HIGH period of this clock pulse.
When SDA remains HIGH during the 9th clock pulse, this is the Not Acknowledge signal. The master can then
generate either a STOP to abort the transfer or a repeated START to start a new transfer.
Slave Address and Data Direction Bit
After the START, a slave address is sent. This address is 7 bits long followed by the eighth bit as a data direction
bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).
Figure 36. Complete Data Transfer
Single Read and Write
Figure 37. Single Write
Figure 38. Single Read
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