Datasheet

bq24190, bq24192
bq24192I, bq24193
SLUSAW5A –JANUARY 2012–REVISED OCTOBER 2012 www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
V
VBUS_UVLOZ
< V
VBUS
< V
ACOV
and V
VBUS
> V
BAT
+ V
SLEEP
, T
J
= –40°C to 125°C and T
J
= 25°C for typical values unless other
noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
BOOST MODE OPERATION
V
OTG_REG
OTG output voltage I(VBUS) = 0 5.00 V
V
OTG_REG_ACC
OTG output voltage accuracy I(VBUS) = 0 –2% 2%
REG01[0] = 0 0.5 A
I
OTG
OTG mode output current
REG01[0] = 1 1.3 A
V
OTG_OVP
OTG over-voltage threshold 5.3 5.5 V
V
OTG_ILIM
LSFET cycle-by-cycle current limit 3.2 4.6 A
V
OTG_HSZCP
HSFET under current falling threshold 100 mA
REG01[0] = 1 1.4 1.8 2.7
I
RBFET_OCP
RBFET over-current threshold A
REG01[0] = 0 0.6 1.1 1.8
REGN LDO
V
VBUS
= 10V, I
REGN
= 40mA 5.6 6 6.4 V
V
REGN
REGN LDO output voltage
V
VBUS
= 5V, I
REGN
= 20mA 4.75 4.8 4.85 V
I
REGN
REGN LDO current limit V
VBUS
= 10V, V
REGN
= 3.8V 50 mA
LOGIC I/O PIN CHARACTERISTICS (OTG, CE, PSEL, STAT, PG)
V
ILO
Input low threshold 0.4 V
V
IH
Input high threshold 1.3 V
V
OUT_LO
Output low saturation voltage Sink current = 5 mA 0.4 V
I
BIAS
High level leakage current Pull up rail 1.8V 1 µA
I
2
C INTERFACE (SDA, SCL, INT)
V
IH
Input high threshold level VPULL-UP = 1.8V, SDA and SCL 1.3 V
V
IL
Input low threshold level VPULL-UP = 1.8V, SDA and SCL 0.4 V
V
OL
Output low threshold level Sink current = 5mA 0.4 V
I
BIAS
High-level leakage current VPULL-UP = 1.8V, SDA and SCL 1 µA
f
SCL
SCL clock frequency 400 kHz
DIGITAL CLOCK AND WATCHDOG TIMER
f
HIZ
Digital crude clock REGN LDO disabled 15 35 50 kHz
f
DIG
Digital clock REGN LDO enabled 1300 1500 1700 kHz
t
WDT
REG05[5:4]=11 REGN LDO enabled 136 160 sec
TYPICAL CHARACTERISTICS
Table 1. Tables of Figures
FIGURE NO.
CHARGING EFFICIENCY vs. CHARGING CURRENT Figure 5
SYSTEM LIGHT LOAD EFFICIENCY vs SYSTEM LOAD CURRENT Figure 6
BOOST MODE EFFICIENCY vs VBUS LOAD CURRENT Figure 7
SYS VOLTAGE REGULATION vs SYSTEM LOAD Figure 8
BOOST MODE VBUS VOLTAGE REGULATION vs VBUS LOAD CURRENT Figure 9
SYS VOLTAGE vs TEMPERATURE Figure 10
BAT VOLTAGE vs TEMPERATURE Figure 11
INPUT CURRENT LIMIT vs TEMPERATURE Figure 12
CHARGE CURRENT vs TEMPERATURE Figure 13
Power Up from USB100mA (VBAT 3.2V) Figure 14
Power Up with Charge Disabled (VBAT 3.2V) Figure 15
Power Up with Charge Enabled Figure 16
Charge Enable (VBUS 5V) Figure 17
Charge Disable (VBUS 12V) Figure 18
Input Current DPM Response without Battery (VBUS 5V, IIN 3A, Charge Disable) Figure 19
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