Datasheet

bq24165
bq24166
bq24167
SLUSAP4B –DECEMBER 2011–REVISED MARCH 2013 www.ti.com
PIN FUNCTIONS
PIN NUMBER
PIN
bq24165 bq24166/7 I/O DESCRIPTION
NAME
YFF RGE YFF RGE
Input power supply. IN is connected to the external DC supply (AC adapter or
IN A1–A4 21 A1–A4 21 I alternate power source). Bypass IN to PGND with at least a 1μF ceramic
capacitor.
USB Input Power Supply. USB is connected to the external DC supply (AC
USB A5–A7 22 A5–A7 22 I adapter or USB port). Bypass USB to PGND with at least a 1μF ceramic
capacitor.
Reverse Blocking MOSFET and High Side MOSFET Connection Point for
High Power Input. Bypass PMIDI to GND with at least a 4.7μF ceramic
PMIDI B1–B4 20 B1–B4 20 O capacitor. Use caution when connecting an external load to PMIDI. The
PMIDI output is not current limited. Any short on PMIDI will result in damage
to the IC.
Reverse Blocking MOSFET and High Side MOSFET Connection Point for
USB Input. Bypass PMIDU to GND with at least a 4.7μF ceramic capacitor.
PMIDU B5–B7 23 B5–B7 23 O
Use caution when connecting an external load to PMIDU. The PMIDU output
is not current limited. Any short on PMIDU will result in damage to the IC.
SW C1–C7 18 C1–C7 18 O Inductor Connection. Connect to the switched side of the external inductor.
Ground terminal. Connect to the thermal pad (for QFN only) and the ground
PGND D1–D7 16, 17 D1–D7 16, 17 –
plane of the circuit.
IN Input Current Limit Programming Input. Connect a resistor from ILIM to
ILIM E1 15 E1 15 I GND to program the input current limit for IN. The current limit is
programmable from 1A to 2.5A. ILIM has no effect on the USB input.
Input DPM Programming Input. Connect a resistor divider from IN to GND
with VDPM connected to the center tap to program the Input Voltage based
VDPM E3 1 E3 1 I Dynamic Power Management (V
IN
-DPM) threshold. The input current is
reduced to maintain the supply voltage at V
IN
-DPM. See the Input Voltage
based Dynamic Power Management section for a detailed explanation.
Charge Enable Input. CE is used to disable or enable the charge process. A
low logic level (0) enables charging and a high logic level (1) disables
charging. When charging is disabled, the SYS output remains in regulation,
CE – – E4 24 I
but BAT is disconnected from SYS. Supplement mode is still available if the
system load demands cannot be met by the supply. BGATE is high
impedance when CE is high.
IUSB1 E5 4 E5 4 I USB Input Current Limit Programming Inputs. USB1, USB2 and USB3
program the input current limit for the USB input. USB2.0 and USB3.0 current
IUSB2 E6 3 E6 3 I
limits are available for easy implementation of these standards. Table 1
shows the settings for these inputs. USB1, USB2 and USB3 have no effect on
IUSB3 E2 2 E2 2 I
the IN input.
CE1 E4 24 – – I JEITA Compliance Inputs. CE1 and CE2are used to change battery regulation
and charge current regulation to comply with the JEITA charging standard.
The charge voltage can be reduced by 140mV or the charge current may be
CE2 G5 9 – – I
reduced to half the programmed value. See Table 2 for programming details.
High Side MOSFET Gate Driver Supply. Connect a 0.01μF ceramic capacitor
BOOT E7 19 E7 19 I (voltage rating > 10V) from BOOT to SW to supply the gate drive for the high
side MOSFETs.
System Voltage Sense and Charger FET Connection. Connect SYS to the
SYS F1–F4 13, 14 F1–F4 13, 14 I system output at the output bulk capacitors. Bypass SYS locally with at least
10μF. 47μF bypass capacitance is recommended for best transient response.
External Discharge MOSFET Gate Connection. BGATE drives an external P-
Channel MOSFET to provide a very low resistance discharge path. Connect
BGATE F5 10 F5 10 O BGATE to the gate of the external MOSFET. BGATE is low during high
impedance mode and when no input is connected. BGATE is optional. If
unused, leave BGATE unconnected.
Power Good Open Drain Output. PG is pulled low when a valid supply is
connected to either USB or IN. A valid supply is between V
BAT
+V
SLP
and
PG F6 7 F6 7 O
V
OVP
. If not supply is connected or the supply is out of this range, PG is high
impedance.
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