Datasheet

bq24155
www.ti.com SLUS942 –FEBRUARY 2010
ELECTRICAL CHARACTERISTICS (continued)
Circuit of Figure 1, VBUS = 5 V, HZ_MODE = 0, OPA_MODE = 0 (charger mode operation), T
J
= 0°C to 125°C, T
J
= 25°C for
typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
REF
output short current limit 30 mA
BATTERY RECHARGE THRESHOLD
V
(RCH)
Recharge threshold voltage Below V
(OREG)
100 120 150 mV
V
(AUXPWR)
decreasing below threshold,
Deglitch time 130 ms
t
FALL
= 100ns, 10 mV overdrive
STAT OUTPUTS
Low-level output saturation
I
O
= 10 mA, sink current 0.4 V
voltage, STAT
V
OL(STAT)
High-level leakage current for
Voltage on STAT pin is 5 V 1 mA
STAT
I
2
C BUS LOGIC LEVELS AND TIMING CHARACTERISTICS
V
OL
Output low threshold level I
O
= 10 mA, sink current 0.4 V
V
IL
Input low threshold level 0.4 V
V
IH
Input high threshold level 1.2 V
I
(BIAS)
Input bias current V
(pull-up)
= 1.8 V, SDA and SCL 1 mA
f
(SCL)
SCL clock frequency 3.4 MHz
BATTERY DETECTION
Battery detection current before Begins after termination detected,
–0.45 mA
charge done (sink current)
(1)
V
(AUXPWR)
≤ V
(OREG)
I
(DETECT)
Battery detection time 262 ms
SLEEP COMPARATOR
Sleep-mode entry threshold,
V
(SLP)
2.3 V ≤ V
(AUXPWR)
≤ V
(OREG)
, V
BUS
falling 0 40 100 mV
V
BUS
- V
AUXPWR
Sleep-mode exit hysteresis 2.3 V ≤ V
(AUXPWR)
≤ V
(OREG)
40 100 160 mV
V
(SLP_EXIT)
Deglitch time for VBUS rising
Rising voltage, 2-mV overdrive, t
RISE
= 100ns 30 ms
above V
(SLP)
+ V
(SLP_EXIT)
UNDERVOLTAGE LOCKOUT
UVLO IC active threshold voltage VBUS rising 3.05 3.3 3.55 V
UVLO
(HYS)
IC active hysteresis VBUS falling from above UVLO 120 150 mV
PWM
Voltage from BOOT pin to SW
During charge or boost operation 6.5 V
pin
Internal top reverse blocking FET I
IN(LIMIT)
= 500 mA, Measured from VBUS to
180 250
on-resistance PMID
Internal top N-channel Switching
Measured from PMID to SW, V
BOOT
- V
SW
= 4 V 120 250 mΩ
FET on-resistance
Internal bottom N-channel FET
Measured from SW to PGND 110 200
on-resistance
f
(OSC)
Oscillator frequency 3 MHz
Frequency accuracy –10% 10%
D
(MAX)
Maximum duty cycle 99.5%
D
(MIN)
Minimum duty cycle 0
Synchronous mode to
non-synchronous mode transition Low side FET cycle by cycle current sensing 100 mA
current threshold
(2)
CHARGE MODE PROTECTION
Input VBUS OVP threshold Threshold over VBUS to turn off converter during
6.3 6.5 6.7 V
voltage charge
V
(OVP-IN)
V
(OVP_IN)
hysteresis VBUS falling from above V
(OVP_IN)
140 mV
V
(CSOUT)
threshold over V
(OREG)
to turn off charger
Output OVP threshold voltage 110 117 121
during charge
V
(OVP)
%V
(OREG)
V
(OVP)
hysteresis Lower limit for V
(CSOUT)
falling from above V
(OVP)
11
(1) Negative charge current means the charge current flows from the battery to charger (discharging battery).
(2) Bottom N-channel FET always turns on for Ⅹ60 ns and then turns off if current is too low.
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