Datasheet

bq24155
SLUS942 –FEBRUARY 2010 www.ti.com
ELECTRICAL CHARACTERISTICS
Circuit of Figure 1, VBUS = 5 V, HZ_MODE = 0, OPA_MODE = 0 (charger mode operation), T
J
= 0°C to 125°C, T
J
= 25°C for
typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT CURRENTS
VBUS > VBUS(min), PWM switching 10 mA
VBUS > VBUS(min), PWM NOT switching 5
0°C < T
J
< 85°C, VBUS = 5 V, HZ_MODE = 1,
V
(AUXPWR)
> V
(LOWV)
, SCL, SDA, ISEL = 0 V or 20 mA
I
(VBUS)
VBUS supply current control
1.8 V
0°C < T
J
< 85°C, VBUS = 5 V, HZ_MODE = 1,
V
(AUXPWR)
< V
(LOWV)
, 32 S mode, SCL, SDA, ISEL 35 mA
= 0 V or 1.8 V
Leakage current from battery to 0°C < T
J
< 85°C, V
(AUXPWR)
= 4.2 V, High
I
lkg
5 mA
VBUS pin impedance mode
0°C < T
J
< 85°C, V
(AUXPWR)
= 4.2 V, High
Battery discharge current in High
impedance mode,
Impedance mode, (CSIN, 20 mA
VBUS = 0 V,
CSOUT, AUXPWR, SW pins)
SCL, SDA, ISEL = 0 V or 1.8 V
VOLTAGE REGULATION
V
(OREG)
Output charge voltage Operating in voltage regulation, programmable 3.5 4.44 V
T
A
= 25°C –0.5% 0.5%
Voltage regulation accuracy
–1% 1%
CURRENT REGULATION (FAST CHARGE)
Output charge current V
(LOWV)
≤ V
(AUXPWR)
< V
(OREG)
, VBUS > V
(SLP)
, 550
I
O(CHARGE)
1250 mA
programmable range R
(SNS)
= 68 mΩ Programmable
Regulation accuracy for charge 20 mV ≤ V
(IREG)
≤ 40 mV –5% 5%
current across R
(SNS)
40 mV < V
(IREG)
–3% 3%
V
(IREG)
= I
O(CHARGE)
× R
(SNS)
WEAK BATTERY DETECTION
V
(LOWV)
Weak battery voltage threshold Programmable 3.4 3.7 V
programmable range
Weak battery voltage accuracy –5% 5%
Hysteresis for V
(LOWV)
Battery voltage falling 100 mV
Deglitch time for weak battery Rising voltage, 2 mV overdrive, t
RISE
= 100 ns
30 ms
threshold
ISEL PIN LOGIC LEVEL
V
IL
Input low threshold level 0.4 V
V
IH
Input high threshold level 1.3 V
CHARGE TERMINATION DETECTION
Termination charge current V
(AUXPWR)
> V
(OREG)
– V
(RCH)
, mA
I
(TERM)
50 400
programmable range VBUS > V
(SLP)
, R
(SNS)
= 68 mΩ Programmable
Deglitch time for charge Both rising and falling, 2 mV overdrive, t
RISE
, t
FALL
30 ms
termination = 100 ns
3.4 mV ≤ V
(IREG_TERM)
< 6.8 mV –25% 25%
Voltage regulation accuracy for
termination current across R
(SNS)
6.8 mV ≤ V
(IREG_TERM)
< 13.6 mV –10% 10%
V
(IREG_TERM)
= I
O(TERM)
× R
(SNS)
13.6 mV ≤ V
(IREG_TERM)
≤ 27.2 mV –5% 5%
INPUT POWER SOURCE DETECTION
Input voltage lower limit Input power source detection, Input voltage falling 3.6 3.8 4 V
Deglitch time for VBUS rising ms
V
IN
(min) Rising voltage, 2 mV overdrive, t
RISE
= 100 ns 30
above V
IN
(min)
Hysteresis for V
IN
(min) Input voltage rising 100 200 mV
t
INT
Detection Interval Input power source detection 2 S
INPUT CURRENT LIMITING
I
IN
= 100 mA 88 93 98 mA
I
IN
Input current limiting threshold USB charge mode
I
IN
= 500 mA 450 475 500
VREF BIAS REGULATOR
VBUS >V
IN
(min) or V
(AUXPWR)
> V
(BAT)
min, V
V
REF
Internal bias regulator voltage 2 6.5
I(VREF) = 1 mA, C(VREF) = 1 mF
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