Datasheet

S SLAVE ADDRESS R/W A REGISTER ADDRESS A DATA

A/A

Data Transferred

‘0’ (Write) (n Bytes+ Acknowledge)

FrommastertotheIC A = Acknowledge(SDA LOW)

A = Notacknowledge(SDA

HIGH)

FromtheICtomaster S =STARTcondition

Sr =RepeatedSTARTcondition

P =STOP condition

(a) F/S-Mode

F/S-Mode HS-Mode

S HS-MASTERCODE

Sr SLAVE ADDRESS R/W A REGISTER ADDRESS A DATA

A/A

Data Transferred

‘0’ (write) (n Bytes+ Acknowledge)

Sr Slave A.

(b)HS- Mode

F/S-Mode

HS-Mode

Continues

bq24155

SLUS942 –FEBRUARY 2010

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Figure 19. Data Transfer Format in F/S Mode and H/S Mode

Slave Address Byte

MSB LSB

X 1 1 0 1 0 1 1

The slave address byte is the first byte received following the START condition from the master device. The

address bits are factory preset to ‘1101011’.

MSB LSB

0 0 0 0 0 D2 D1 D0

Following the successful acknowledgment of the slave address, the bus master will send a byte to the bq24155,

which contains the address of the register to be accessed. The bq24155 contains five 8-bit registers accessible

via a bidirectional I

C-bus interface. Among them, four internal registers have read and write access; and one

has only read access.

Product Folder Link(s): bq24155