Datasheet

3
2
1 14
7 8
4
6
5
11
12
13
9
10
PMID
Thermal
Pad
SW
PGND
SGND
BOOT
VBUS
CSIN
AUXPWR VREF
SCL
SDA
STAT
ISEL
CSOUT
bq24155
SLUS942 –FEBRUARY 2010 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION CONTINUED
During the charging process, the bq24155 monitors its junction temperature (T
J
) and reduces the charge current
once T
J
increases to approximately 125°C. The bq24155 is available in 14-pin QFN package.
RGY PACKAGE
(Top View)
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTION
NAME NO.
Battery voltage and current sense input. Bypass it with a ceramic capacitor (minimum 0.1 mF) to
CSOUT 6 I
PGND if there are long inductive leads to battery.
VBUS 14 I Charger input voltage. Bypass it with a 1-mF ceramic capacitor from VBUS to PGND.
Connection point between reverse blocking FET and high-side switching FET. Bypass it with a
PMID 13 O
minimum of 3.3-mF capacitor from PMID to PGND.
SW 12 O Internal switch to output inductor connection.
Bootstrap capacitor connection for the high-side FET gate driver. Connect a 10-nF ceramic capacitor
BOOT 1 O
(voltage rating above 10 V) from BOOT pin to SW pin.
PGND 11 Power ground
Charge current-sense input. Battery current is sensed across an external sense resistor. A 0.1-mF
CSIN 9 I
ceramic capacitor to PGND is required.
SCL 2 I
I
2
C interface clock. Open drain output, connect a 10-kΩ pullup resistor to 1.8V rail
SDA 3 I/O
I
2
C interface data. Open drain output, connect a 10-kΩ pullup resistor to 1.8V rail
Charge status pin. Pull low when charge in progress. Open drain for other conditions. During faults, a
STAT 4 O 128mS pulse is sent out. STAT pin can be disabled by the EN_STAT bit in control register. STAT can
be used to drive a LED or communicate with a host processor.
Internal bias regulator voltage. Connect a 1-mF ceramic capacitor from this output to PGND. External
VREF 8 O
load on VREF is not allowed.
Auxiliary power supply, connected to the battery pack to provide power in high-impedance mode.
AUXPWR 7 I
Bypass it with a 1-mF ceramic capacitor from this pin to PGND.
Input current limiting selection pin. In 32 minutes mode, the ISEL pin is default to be used as the input
ISEL 5 I current limiting selection pin. When ISEL = High, Iin – limit = 500 mA and when ISEL = Low, Iin – limit
= 100 mA, see the Control Register for details.
SGND 10 - Signal ground
There is an internal electrical connection between the exposed thermal pad and the PGND pin of the
device. The thermal pad must be connected to the same potential as the PGND pin on the printed
Thermal pad pad -
circuit board. Do not use the thermal pad as the primary ground input for the device. PGND/SGND
must be connected to ground at all times.
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