Datasheet

SDA
SCL
RecognizeSTARTor
REPRATEDSTART
Condition
RecognizeSTOP or
REPRATEDSTART
Condition
Generate ACKNOWLEDGE
Signal
Acknowledgement
SignalFromSlave
MSB
Address
R/W
ACK
ClockLineHeldLowWhile
InterruptsareServiced
S
or
Sr
Sr
or
P
P
Sr
ACK
bq24155
www.ti.com SLUS942 –FEBRUARY 2010
Figure 18. Bus Protocol
H/S Mode Protocol
When the bus is idle, both SDA and SCL lines are pulled high by the pull-up devices.
The master generates a start condition followed by a valid serial byte containing HS master code '00001XXX'.
This transmission is made in F/S mode at no more than 400 Kbps. No device is allowed to acknowledge the HS
master code, but all devices must recognize it and switch their internal setting to support 3.4-Mbps operation
The master then generates a repeated start condition (a repeated start condition has the same timing as the start
condition). After this repeated start condition, the protocol is the same as F/S mode, except that transmission
speeds up to 3.4 Mbps are allowed. A stop condition ends the HS mode and switches all the internal settings of
the slave devices to support the F/S mode. Instead of using a stop condition, repeated start conditions should be
used to secure the bus in HS mode. If a transaction is terminated prematurely, the master needs sending a
STOP condition to prevent the slave I
2
C logic from remaining in a bad state.
Attempting to read data from register addresses not listed in this section results in FFh being read out.
bq24155 I
2
C Update Sequence
The bq24155 requires a start condition, a valid I
2
C address, a register address byte, and a data byte for a single
update. After the receipt of each byte, bq24155 device acknowledges by pulling the SDA line low during the high
period of a single clock pulse. A valid I
2
C address selects the bq24155. The bq24155 performs an update on the
falling edge of the acknowledge signal that follows the LSB byte.
For the first update, bq24155 requires a start condition, a valid I
2
C address, a register address byte, a data byte.
For all consecutive updates, bq24155 needs a register address byte, and a data byte. Once a stop condition is
received, the bq24155 releases the I
2
C bus, and awaits a new start conditions.
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