Datasheet

DATA
CLK
DataLine
Stable;
DataValid
Change
ofData
Allowed
DataOutput
byTransmitter
DataOutput
byReceiver
SCL From
Master
Not Acknowledge
Acknowledge
ClockPulsefor
Acknowledgement
1 2
8
9
START
Condition
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SLUS942 –FEBRUARY 2010 www.ti.com
Figure 16. Bit Transfer on the Serial Interface
The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the
slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. the 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line
from low to high while the SCL line is high (see Figure 18). This releases the bus and stops the communication
link with the addressed slave. All I
2
C compatible devices must recognize the stop condition. Upon the receipt of a
stop condition, all devices know that the bus is released, and wait for a start condition followed by a matching
address. If a transaction is terminated prematurely, the master needs sending a STOP condition to prevent the
slave I
2
C logic from remaining in a bad state. Attempting to read data from register addresses not listed in this
section will result in FFh being read out.
Figure 17. Acknowledge on the I
2
C Bus™
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