Datasheet

bq20z95
www.ti.com SLUS757C –JULY 2007–REVISED OCTOBER 2013
DATA FLASH CHARACTERISTICS (Over Recommended Operating Temperature and Supply
Voltage) (continued)
Typical Values at T
A
= 25°C and V
(REG25)
= 2.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Data retention 10 Years
Flash programming write-cycles 20k Cycles
t
(ROWPROG)
Row programming time See
(1)
2 ms
t
(MASSERASE)
Mass-erase time 200 ms
t
(PAGEERASE)
Page-erase time 20 ms
I
(DDPROG)
Flash-write supply current 5 10 mA
I
(DDERASE)
Flash-erase supply current 5 10 mA
RAM BACKUP
V
(RBI)
> V
(RBI)MIN
, V
REG25
< V
IT–
,
1000 2500
T
A
= 85°C
I
(RB)
RB data-retention input current nA
V
(RBI)
> V
(RBI)MIN
, V
REG25
< V
IT–
,
90 220
T
A
= 25°C
V
(RB)
RB data-retention input voltage
(1)
1.7 V
(1) Specified by design. Not production tested.
SMBUS TIMING CHARACTERISTICS
T
A
= –40°C to 85°C Typical Values at T
A
= 25°C and V
REG25
= 2.5 V (Unless Otherwise Noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
(SMB)
SMBus operating frequency SLAVE mode, SMBC 50% duty cycle 10 100 kHz
f
(MAS)
SMBus master clock frequency MASTER mode, No clock low slave extend 51.2 kHz
Bus free time between start and stop
t
(BUF)
4.7 µs
(see Figure 1)
t
(HD:STA)
Hold time after (repeated) start (see 4 µs
Figure 1)
t
(SU:STA)
Repeated start setup time (see Figure 1) 4.7 µs
t
(SU:STO)
Stop setup time (see Figure 1) 4 µs
t
(HD:DAT)
RECEIVE mode 0 ns
Data hold time (see Figure 1)
TRANSMIT mode 300
t
(SU:DAT)
Data setup time (see Figure 1) 250 ns
t
(TIMEOUT)
Error signal/detect (see Figure 1) See
(1)
25 35 µs
t
(LOW)
Clock low period (see Figure 1) 4.7 µs
t
(HIGH)
Clock high period (see Figure 1) See
(2)
4 50 µs
t
(LOW:SEXT)
Cumulative clock low slave extend time See
(3)
25 µs
Cumulative clock low master extend time
t
(LOW:MEXT)
See
(4)
10 µs
(see Figure 1)
t
f
Clock/data fall time See
(5)
300 ns
t
r
Clock/data rise time See
(6)
1000 ns
(1) The bq20z95 times out when any clock low exceeds t
(TIMEOUT)
.
(2) t
(HIGH)
, Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction involving bq20z95 that is in
progress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0]=0).
(3) t
(LOW:SEXT)
is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
(4) t
(LOW:MEXT)
is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop.
(5) Rise time t
r
= VILMAX – 0.15) to (VIHMIN + 0.15)
(6) Fall time t
f
= 0.9V
DD
to (VILMAX – 0.15)
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Links: bq20z95