Datasheet

bq20z95
SLUS757C –JULY 2007–REVISED OCTOBER 2013 www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted), T
A
= –40°C to 85°C, V
(REG25)
= 2.41 V to 2.59 V, V
(BAT)
=
14 V, C
(REG25)
= 1 µF, C
(REG33)
= 2.2 µF; typical values at T
A
= 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
WDWT
Watchdog detect time 50 100 150 µs
2.5V LDO; I
(REG33OUT)
= 0 mA; T
A
= 25°C (unless otherwise noted)
4.5 < VCC or BAT < 25 V;
V
(REG25)
Regulator output voltage I
(REG25OUT
) ≤ 16 mA; 2.41 2.5 2.59 V
T
A
= –40°C to 100°C
Regulator output change with I
(REG25OUT)
= 2 mA;
ΔV
(REG25TEMP)
±0.2 %
temperature T
A
= –40°C to 100°C
5.4 < VCC or BAT < 25 V;
ΔV
(REG25LINE)
Line regulation 3 10 mV
I
(REG25OUT)
= 2 mA
0.2 mA ≤ I
(REG25OUT)
≤ 2 mA 7 25
ΔV
(REG25LOAD)
Load Regulation mV
0.2 mA ≤ I
(REG25OUT)
≤ 16 mA 25 50
Drawing current until
I
(REG25MAX)
Current Limit 5 40 75 mA
REG25 = 2 V to 0 V
3.3V LDO; I
(REG25OUT)
= 0 mA; T
A
= 25°C (unless otherwise noted)
4.5 < VCC or BAT < 25 V;
V
(REG33)
Regulator output voltage I
(REG33OUT)
≤ 25 mA; 3 3.3 3.6 V
T
A
= –40°C to 100°C
Regulator output change with I
(REG33OUT)
= 2 mA;
ΔV
(REG33TEMP)
±0.2 %
temperature T
A
= –40°C to 100°C
5.4 < VCC or BAT < 25 V;
ΔV
(REG33LINE)
Line regulation 3 10 mV
I
(REG33OUT)
= 2 mA
0.2 mA ≤ I
(REG33OUT)
≤ 2 mA 7 17
ΔV
(REG33LOAD)
Load Regulation mV
0.2mA ≤ I
(REG33OUT)
≤ 25 mA 40 100
Drawing current until REG33 = 3 V 25 100 145
I
(REG33MAX)
Current Limit mA
Short REG33 to VSS, REG33 = 0 V 12 65
THERMISTOR DRIVE
V
(TOUT)
Output voltage I
(TOUT)
= 0 mA; T
A
= 25°C V
(REG25)
V
I
(TOUT)
= 1 mA; R
DS(on)
= (V
(REG25)
– V
(TOUT)
)/1 mA; T
A
=
R
DS(on)
TOUT pass element resistance 50 100 Ω
–40°C to 100°C
VCELL+ HIGH VOLTAGE TRANSLATION
VC(n) – VC(n+1) = 0 V;
0.950 0.975 1
T
A
= –40°C to 100°C
V
(VCELL+OUT)
VC(n) – VC(n+1) = 4.5 V;
0.275 0.3 0.375
T
A
= –40°C to 100°C
internal AFE reference voltage;
V
(VCELL+REF)
0.965 0.975 0.985
Translation output T
A
= –40°C to 100°C V
0.98 × 1.02 ×
Voltage at PACK pin; V
(PACK)
/1
V
(VCELL+PACK)
V
(PACK)
/1 V
(PACK)
/1
T
A
= –40°C to 100°C 8
8 8
Voltage at BAT pin; 0.98 × 1.02 ×
V
(VCELL+BAT)
V
(BAT)
/18
T
A
= –40°C to 100°C V
(BAT)
/18 V
(BAT)
/18
CMMR Common mode rejection ratio VCELL+ 40 dB
K= {VCELL+ output (VC5=0 V; VC4=4.5 V) – VCELL+
0.147 0.150 0.153
output (VC5=0 V; VC4=0 V)}/4.5
K Cell scale factor
K= {VCELL+ output (VC2=13.5V; VC1=18 V) – VCELL+
output 0.147 0.150 0.153
(VC5=13.5 V; VC1=13.5 V)}/4.5
VC(n) – VC(n+1) = 0V; VCELL+ = 0 V;
I
(VCELL+OUT)
Drive Current to VCELL+ capacitor 12 18 μA
T
A
= –40°C to 100°C
CELL output (VC2 = VC1 = 18 V) – CELL output (VC2 =
V
(VCELL+O)
CELL offset error –18 –1 18 mV
VC1 = 0 V)
I
VCnL
VC(n) pin leakage current VC1, VC2, VC3, VC4, VC5 = 3 V –1 0.01 1 μA
CELL BALANCING
Internal cell balancing FET R
DS(on)
for internal FET switch at
R
BAL
200 400 600 Ω
resistance V
DS
= 2 V; T
A
= 25°C
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