Datasheet

bq20z95
www.ti.com SLUS757C –JULY 2007–REVISED OCTOBER 2013
TERMINAL FUNCTIONS
TERMINAL
I/O
(1)
DESCRIPTION
NO. NAME
1 DSG O High-side N-chan discharge FET gate drive
Battery pack input voltage sense input. It also serves as device wake up when device is in
2 PACK IA, P
SHUTDOWN mode.
Positive device supply input. Connect to the center connection of the CHG FET and DSG FET to
3 VCC P
ensure device supply either from battery stack or battery pack input.
4 ZVCHG O P-chan pre-charge FET gate drive
High voltage general purpose open drain output. Can be configured to be used in pre-charge
5 GPOD OD
condition.
PRE-CHARGE mode setting input. Connect to PACK to enable 0-V pre-charge using charge FET
6 PMS I connected at CHG pin. Connect to VSS to disable 0-V pre-charge using charge FET connected at
CHG pin.
7 VSS P Negative device power supply input. Connect all VSS pins together for operation of device.
8 REG33 P 3.3-V regulator output. Connect at least a 2.2-μF capacitor to REG33 and VSS.
9 TOUT P Thermistor bias supply output
Internal cell voltage multiplexer and amplifier output. Connect a 0.1-μF capacitor to VCELL+ and
10 VCELL+ —
VSS.
Alert output. In case of short circuit condition, overload condition and watchdog time out this pin will
11 ALERT I/OD
be triggered.
12 NC — Not connected
13 TS1 IA Temperature sensor 1 input
14 TS2 IA Temperature sensor 2 input
15 PRES I/OD System/Host present input
16 PFIN I/OD Fuse blow detection input
17 SAFE I/OD Blow fuse signal output
18 SMBD I/OD SMBus data line
19 NC — Not connected
20 SMBC I/OD SMBus clock line
21 DISP I/OD Display enable input
22 VSS P Negative device power supply input. Connect all VSS pins together for operation of device.
23 LED1 I LED 1 current sink input
24 LED2 I LED 2 current sink input
25 LED3 I LED 3 current sink input
26 LED4 I LED 4 current sink input
27 LED5 I LED 5 current sink input
28 GSRP IA Coulomb counter differential input. Connect to one side of the sense resistor.
29 GSRN IA Coulomb counter differential input. Connect to one side of the sense resistor.
30 MRST I Reset input for internal CPU core. Connect to RESET for correct operation of device.
31 VSS P Negative device power supply input. Connect all VSS pins together for operation of device.
32 REG25 P 2.5-V regulator output. Connect at least a 1-μF capacitor to REG25 and VSS.
RAM backup input. Connect a capacitor to this pin and VSS to protect loss of RAM data in case of
33 RBI P
short circuit condition.
34 VSS P Negative device power supply input. Connect all VSS pins together for operation of device.
35 RESET O Reset output. Connect to MSRT.
36 ASRN IA Short circuit and overload detection differential input. Connect to sense resistor.
37 ASRP IA Short circuit and overload detection differential input. Connect to sense resistor.
Cell voltage sense input and cell balancing input for the negative voltage of the bottom cell in cell
38 VC5 IA, P
stack.
Cell voltage sense input and cell balancing input for the positive voltage of the bottom cell and the
39 VC4 IA, P
negative voltage of the second lowest cell in cell stack.
(1) I = Input, IA = Analog input, I/O = Input/output, I/OD = Input/Open-drain output, O = Output, OA = Analog output, P = Power
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