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SMBus TIMING SPECIFICATIONS
bq20z80-V102
SLUS681B – NOVEMBER 2005 – REVISED JANUARY 2007
V
DD
= 3 V to 3.6 V, T
A
= –40 ° C to 85 ° C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
SMB
SMBus operating frequency Slave mode, SMBC 50% duty cycle 10 100
kHz
f
MAS
SMBus master clock frequency Master mode, no clock low slave extend 51.2
t
BUF
Bus free time between start and stop 4.7
t
HD:STA
Hold time after (repeated) start 4
µ s
t
SU:STA
Repeated start setup time 4.7
t
SU:STO
Stop setup time 4
Receive mode 0
t
HD:DAT
Data hold time
Transmit mode 300 ns
t
SU:DAT
Data setup time 250
t
TIMEOUT
Error signal/detect See
(1)
25 35 ms
t
LOW
Clock low period 4.7
µ s
t
HIGH
Clock high period See
(2)
4 50
t
LOW:SEXT
Cumulative clock low slave extend time See
(3)
25
ms
t
LOW:MEXT
Cumulative clock low master extend time See
(4)
10
t
F
Clock/data fall time (V
ILMAX
– 0.15 V) to (V
IHMIN
+ 0.15 V) 300
ns
t
R
Clock/data rise time 0.9 VDD to (VILMAX – 0.15 V) 1000
(1) The bq20z80 times out when any clock low exceeds t
TIMEOUT
.
(2) t
HIGH:MAX
. is minimum bus idle time. SMBC = 1 for t > 50 µ s causes reset of any transaction involving the bq20z80 that is in progress.
(3) t
LOW:SEXT
is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
(4) t
LOW:MEXT
is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop.
SMBus TIMING DIAGRAM
7
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