Datasheet

t
(LOW)
t
f
t
r
t
(HD:STA)
t
(SU:DAT)
t
(HIGH)
t
(HD:DAT)
t
(HD:STA)
t
(BUF)
SCLK
SDATA
t
(SU:STO)
P
SS
P
SCLK
SDATA
Start Stop
t
(LOW:SEXT)
t
(LOW:MEXT)
t
(LOW:MEXT)
t
(LOW:MEXT)
SCLK
ACK
(1)
SCLK
ACK
(1)
t
(SU:STA)
bq20z75-V180
SLUSA22 –DECEMBER 2009 www.ti.com
SMBus Timing Characteristics (continued)
T
A
= –40°C to 85°C Typical Values at T
A
= 25°C and V
(REG25)
= 2.5 V (Unless Otherwise Noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
(TIMEOUT)
Error signal/detect (see Figure 1) See
(1)
25 35 µs
t
(LOW)
Clock low period (see Figure 1) 4.7 µs
t
(HIGH)
Clock high period (see Figure 1) See
(2)
4.0 50 µs
t
(LOW:SEXT)
Cumulative clock low slave extend time See
(3)
25 µs
t
(LOW:MEXT)
Cumulative clock low master extend time (see See
(4)
10 µs
Figure 1)
t
f
Clock/data fall time See
(5)
300 ns
t
r
Clock/data rise time See
(6)
1000 ns
(1) The bq20z75-V180 times out when any clock low exceeds t
(TIMEOUT)
.
(2) t
(HIGH)
, Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction involving bq20z75-V180
that is in progress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0]=0).
(3) t
(LOW:SEXT)
is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
(4) t
(LOW:MEXT)
is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop.
(5) Rise time t
r
= VILMAX – 0.15) to (VIHMIN + 0.15)
(6) Fall time t
f
= 0.9V
DD
to (VILMAX – 0.15)
(1) SCLK
ACK
is the acknowledge-related clock pulse generated by the master.
Figure 1. SMBus Timing Diagram
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