Datasheet

SMBC
SMBD
SMBC
SMBD
SMBC
SMBD
S
t
SU(STA)
SP
t
BUF
t
SU(STO)
t
R
t
F
SMBC
SMBD
t
TIMEOUT
t
HIGH
t
LOW
t
F
t
R
t
HD(DAT)
t
SU(DAT)
t
HD(STA)
Start and Stop condition Wait and Hold condition
Timeout condition Repeated Start condition
bq20z65-R1
www.ti.com SLUS990 –DECEMBER 2009
A. SCLKACK is the acknowledge-related clock pulse generated by the master.
Figure 1. SMBus Timing Diagram
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): bq20z65-R1