Datasheet

bq20z45
SLUS800 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted), T
A
= – 40 ° C to 85 ° C, V
(REG25)
= 2.41 V to 2.59 V,
V
(BAT)
= 14 V, C
(REG25)
= 1 µ F, C
(REG33)
= 2.2 µ F; typical values at T
A
= 25 ° C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
drawing current until REG33 = 3 V 25 100 145
I
(REG33MAX)
Current Limit mA
short REG33 to VSS, REG33 = 0 V 12 65
THERMISTOR DRIVE
V
(TOUT)
Output voltage I
(TOUT)
= 0 mA; T
A
= 25 ° C V
(REG25)
V
I
(TOUT)
= 1 mA; R
DS(on)
= (V
(REG25)
-
R
DS(on)
TOUT pass element resistance 50 100 Ω
V
(TOUT)
)/ 1 mA; T
A
= – 40 ° C to 100 ° C
VCELL+ HIGH VOLTAGE TRANSLATION
VC(n) - VC(n+1) = 0 V;
0.950 0.975 1
T
A
= – 40 ° C to 100 ° C
V
(VCELL+OUT)
VC(n) - VC(n+1) = 4.5 V;
0.275 0.3 0.375
T
A
= – 40 ° C to 100 ° C
internal AFE reference voltage ;
V
(VCELL+REF)
Translation output 0.965 0.975 0.985 V
T
A
= – 40 ° C to 100 ° C
Voltage at PACK pin; 0.98 × 1.02 ×
V
(VCELL+PACK)
V
(PACK)
/18
T
A
= – 40 ° C to 100 ° C V
(PACK)
/18 V
(PACK)
/18
Voltage at BAT pin; 0.98 ×
V
(VCELL+BAT)
V
(BAT)
/18 1.02 × V
(BAT)
/18
T
A
= – 40 ° C to 100 ° C V
(BAT)
/18
CMMR Common mode rejection ratio VCELL+ 40 dB
K= {VCELL+ output (VC5=0V;
VC4=4.5V) - VCELL+ output (VC5=0V; 0.147 0.150 0.153
VC4=0V)}/4.5
K Cell scale factor
K= {VCELL+ output (VC2=13.5V;
VC1=18V) - VCELL+ output 0.147 0.150 0.153
(VC5=13.5V; VC1=13.5V)}/4.5
VC(n) - VC(n+1) = 0V; VCELL+ = 0 V;
I
(VCELL+OUT)
Drive Current to VCELL+ capacitor 12 18 µ A
T
A
= – 40 ° C to 100 ° C
CELL output (VC2 = VC1 = 18 V) -
V
(VCELL+O)
CELL offset error -18 -1 18 mV
CELL output (VC2 = VC1 = 0 V)
I
VCnL
VC(n) pin leakage current VC1, VC2, VC3, VC4, VC5 = 3 V -1 0.01 1 µ A
CELL BALANCING
R
DS(on)
for internal FET switch at
R
(BAL)
internal cell balancing FET resistance 200 400 600 Ω
V
DS
= 2 V; T
A
= 25 ° C
HARDWARE SHORT CIRCUIT AND OVERLOAD PROTECTION; T
A
= 25 ° C (unless otherwise noted)
V
OL
= 25 mV (min) 15 25 35
OL detection threshold voltage
V
(OL)
V
OL
= 100 mV; RSNS = 0, 1 90 100 110 mV
accuracy
V
OL
= 205 mV (max) 185 205 225
V
(SCC)
= 50 mV (min) 30 50 70
SCC detection threshold voltage
V
(SCC)
V
(SCC)
= 200 mV; RSNS = 0, 1 180 200 220 mV
accuracy
V
(SCC)
= 475 mV (max) 428 475 523
V
(SCD)
= – 50 mV (min) – 30 – 50 – 70
SCD detection threshold voltage
V
(SCD)
V
(SCD)
= – 200 mV; RSNS = 0, 1 – 180 – 200 – 220 mV
accuracy
V
(SCD)
= – 475 mV (max) – 428 – 475 – 523
t
da
Delay time accuracy ± 15.25 µ s
t
pd
Protection circuit propagation delay 50 µ s
FET DRIVE CIRCUIT; T
A
= 25 ° C (unless otherwise noted)
V
(DSGON)
= V
(DSG)
- V
(PACK)
;
V
(DSGON)
DSG pin output on voltage V
(GS)
= 10 M Ω ; DSG and CHG on; 8 12 16 V
T
A
= – 40 ° C to 100 ° C
V
(CHGON)
= V
(CHG)
- V
(BAT)
;
V
(CHGON)
CHG pin output on voltage V
(GS)
= 10 M Ω ; DSG and CHG on; 8 12 16 V
T
A
= – 40 ° C to 100 ° C
V
(DSGOFF)
DSG pin output off voltage V
(DSGOFF)
= V
(DSG)
- V
(PACK)
0.2 V
V
(CHGOFF)
CHG pin output off voltage V
(CHGOFF)
= V
(CHG)
- V
(BAT)
0.2 V
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