Datasheet

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SYSTEM DIAGRAM
PowerManagement
LDO, TOUT andPowerModeControl
Pre-ChargeControl
Fail-Safe
Protection
TemperatureMeasurement
<1%Error
T
INT
1kBytesof
UserFlash
32kHzClock
Generator
CellBalancing AlgorithmandControl
SBSv1.1Data SystemInterface
bq29312RAM/CommsV alidation
1
st
LevelOC
Protection
1
st
LevelOVand
UVProtection
PackUnder
VoltagePower
ModeControl
CellandPack
Voltage
Measurement
CapacityPrediction<1%Error
Pres
SMBus
bq2084−V143
PCHFET Drive
Pre-Charge
FET Drive
CellBalancing
Drive
LDO, ThermOutputDriveandUVLO
System
Watchdog
DelayCounters
RAMRegistersSystemInterface
PowerModeControl
VoltageLevel T ranslator
bq29312
2-TierOvercurrentProtection
3.3V
T1
I
2
C
PFInput
Discharge/Charge/
Pre-ChargeFETs
2ndLevelOvervoltageProtection
Fuse
Pack+
Pack −
32kHz
SenseResistor
(5to30m Ω)
PIN ASSIGNMENTS
SMBD
1
4
2
5
3
6
7
PU
VSSD
VSSD
LED5
VSSD
LED3
CLKOUT
LED4
N/C
LED2
XCK1/VSSA
DISP
VIN
PFIN
TS
LED1
SMBC
MRST
SAFE
EVENT
N/C
SR2
VSSD
SR1
SDATA
VSSA
RBI
VSSA
VDDD
VDDA
N/C
FIL
T
SCLK
XCK2/ROSC
PRES
8
9
36
10
35
11
34
12
33
13
32
14
31
15
30
16
29
17
28
18
27
26
23
25
22
24
21
20
19
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
VIN
TS
VSSA
PU
PRES
SCLK
NC
VDDD
RBI
SDATA
VSSD
SAFE
NC
NC
SMBC
SMBD
DISP
PFIN
VSSD
VSSD
NC
NC
CLKOUT
XCK1/VSSA
XCK2/ROSC
FILT
VDDA
VSSA
VSSA
SR1
SR2
MRST
EVENT
LED1
LED2
LED3
LED4
LED5
bq2084-V143
SLUS732 – SEPTEMBER 2006
QFN (RTT)
(TOP VIEW)
TSSOP (DBT)
(TOP VIEW)
6
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