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SMBus TIMING DIAGRAMS
bq2084-V143
SLUS732 – SEPTEMBER 2006
SMBus TIMING SPECIFICATIONS (continued)
V
DD
= 3 V to 3.6 V, T
A
= -20 ° C to 85 ° C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
(HIGH)
Clock high period See
(2)
4 50 µs
t
LOW:SEXT)
Cumulative clock low slave extend time See
(3)
25 ms
t
LOW:MEXT
Cumulative clock low master extend time See
(4)
10 ms
t
f
Clock/data fall time (V
ILMAX
– 0.15 V) to (V
IHMIN
+ 0.15 V) 300 ns
t
r
Clock/data rise time 0.9 V
DD
to (V
ILMAX
– 0.15 V) 1000 ns
(2) t
(HIGH)
Max. is minimum bus idle time. SMBC = 1 for t > 50 ms causes reset of any transaction involving bq2084-V143 that is in
progress.
(3) t
(LOW:SEXT)
is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
(4) t
(LOW:MEXT)
is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop.
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