Datasheet

bq2060A
SLUS500D –OCTOBER 2001– REVISED OCTOBER 2011 www.ti.com
PEC Calculation
The basis of the PEC calculation is an 8-bit Cyclic Redundancy Check (CRC-8) based on the polynomial C(X) =
X
8
+X
2
+X
1
+1. The PEC calculation includes all bytes in the transmission, including address, command, and data.
The PEC calculation does not include ACKNOWLEDGE, NOT ACKNOWLEDGE, START, STOP, and Repeated
START bits.
For example, the host requests RemainingCapacity() from the bq2060A. This includes the host following the
Read Word protocol. The bq2060A calculates the PEC based on the following 5 bytes of data, assuming the
remaining capacity of the battery is 1001 mAh.
• Battery Address with R/W= 0: 0x16
• Command Code for RemainingCapacity(): 0x0f
• Battery Address with R/W= 1: 0x17
• RemainingCapacity(): 0x03e9
For 0x160f17e903, the bq2060A transmits a PEC of 0xe8 to the host.
PEC Enable in Master Mode
PEC for master mode broadcasts to the charger, host, or both can be enabled/disabled with the combination of
the bits HPE and CPE in Control Mode.
SMBus On and Off State
The bq2060A detects whether the SMBus enters the Off State by monitoring the SMBC and SMBD lines. When
both signals are continually low for at least 2.5 s, the bq2060A detects the Off State. When the SMBC and
SMBD lines go high, the bq2060A detects the On State and can begin communication within 1 ms. One-MΩ
pulldown resistors on SMBC and SMBD are recommended for reliable Off State detection.
HDQ16
The HDQ16 interface is a command-based protocol. (See Figure 10.) A processor sends the command code to
the bq2060A. The 8-bit command code consists of two fields, the 7-bit HDQ16 command code (bits 0–6) and the
1-bit R/W field. The R/W field directs the bq2060A either to
• Store the next 16 bits of data to a specified register or
• Output 16 bits of data from the specified register
With HDQ16, the least significant bit of a data byte (command) or word (data) is transmitted first.
A bit transmission consists of three distinct sections. The first section starts the transmission by either the host or
the bq2060A taking the HDQ16 pin to a logic-low state for a period t
STRH;B
. The next section is the actual data
transmission, where the data bit is valid by the time, t
DSU;B
after the negative edge used to start communication.
The data bit is held for a period t
DH;DV
to allow the host processor or bq2060A to sample the data bit.
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