Datasheet

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NOTE:IndividualbytesofaddressanddataaretransmittedLSBfirst
WriteMemory
Command?
(0Fh)
Selected
State
Selected
State
BusMaster TransmitsLowByte Address
(LSBFirst) AD0to AD7
BusMaster TransmitsHighByte Address
(LSBFirst) AD8to AD15
bq2022A
Loads AddressInto AddressCounter
bq2022A TransmitsCRCofWriteCommand
and Address,thenClearsCRCRegister
bq2022A Receives8BytesofDataand
StoresinRAMBuffer
bq2022A Transmits
CRCofPreviousReceived8BytesofData
Code5Ah
Received
YN
VoltageonData
Pin=VPP
Y
N
N
Y
ContentsofRAMbuffer AND’edwithcontentsof
datamemoryoffsetby
addresscounterandstoredindata
memoryoffsetbyaddresscounter .
programmingtimerequiredtobeat
leastt
EPROG
whenVPP Vdcondatapin
bq2022A
Transmits1ByteofDataMemory
at AddressCounter
8thByte
Transmitted
Y
N
bq2022A WaitsforReset
(NoFurtherResponse)
bq2022A
Increments Address
Counterand Transmits1
ByteofDataMemory
Indexedby AddressCounter
bq2022A
SLUS724C – SEPTEMBER 2006 – REVISED AUGUST 2007
For both of these cases, the decision to continue programming is made entirely by the host, because the
bq2022A is not able to determine if the 8-bit CRC calculated by the host agrees with the 8-bit CRC calculated by
the bq2022A.
Prior to programming, bits in the 1024-bit EPROM data field appear as logical 1s.
Figure 9. WRITE MEMORY Command Flow
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